• Journal of the Institute of Convergence Signal Processing
• /
• v.4 no.1
• /
• pp.64-70
• /
• 2003

Current growth of VLSI design depends critically on the research and development (If automatic layout tool. Automatic layout is composed of placement assigning a specific shape to a block and arranging the block on the layout surface and routing finding the interconnection of all the nets. Algorithms Performing placement and routing impact on Performance and area of VLSI design. Channel routing is a problem assigning each net to a track after global routing and minimizing the track that assigned each net. In this paper we propose a genetic algorithm searching solution space for the netlist partitioning problem for 4-layer channel routing. We compare the performance of proposed genetic algorithm(GA) for channel routing with that of simulated annealing(SA) algorithm by analyzing the results which are the solution of given problems. Consequently experimental results show that out proposed algorithm reduce area over the SA algorithm.

• Journal of the Korea Computer Industry Society
• /
• v.4 no.12
• /
• pp.943-952
• /
• 2003

GDS(Grating automatic Drawing System), which is an automatic design system of metal products called grating, is a system that produces various detailed drawings on the basis of information within a Plan Drawing that represents layout of the gratings such as locations, shapes, directions, etc. However, automatically produced drawings by GDS do not fully satisfy the standard of the general dimension marking method used among the layout designers. The lack of this standard quality mainly results from the fact that overlapping among dimension markings appears frequently. To solve the overlapping problem we applied the rule-based expert system which uses the expert's knowledges and facts to solve the problems. The rules for the expert system are designed based on the expertise of skilled layout designers within the grating production lines.

• Journal of Drive and Control
• /
• v.10 no.4
• /
• pp.7-13
• /
• 2013

A tractor is a farm vehicle that is designed to provide a high tractive effort at low speed. It is used for versatile agricultural tasks such as hauling a trailer, tillage, mowing and construction work. As the intensity of work increases, tractors equipped with automatic transmission become popular due to the work convenience. Though manual and power shuttle transmissions are produced by domestic corporations, development for full-automatic power shift transmissions has never been challenged, and so related technology level is quite low. This paper gives a survey of the automatic transmissions from advanced foreign company, which includes layout of gear train, the way hydraulics controls clutches and brakes, electronic control system. The results are expected to be utilized as a basis in the development of original power train design for tractor.

• Transactions of the Korean Society of Machine Tool Engineers
• /
• v.11 no.6
• /
• pp.38-44
• /
• 2002

Today most companies are designing their automobile shapes by using 3 dimensional CAD software, CATIA. And they used to design 2 dimensional press dies to do some elastic work on their products, but they are currently trying to make use of 3 dimensional software, Pro-Engineer. In this case, they have to change the 3 dimensional product design data to the proper format data for the following process. This paper will show the data loss and the deformation during data transfer between CATIA and Pro-Engineer, and then suggest a solution for these problems. Product's surface will be automatically placed by automatic press tipping angle setting in CATIA to prevent the product from being stuck m the press die. The 2 dimensional section view which is based on the tipping angle setting is created by Z-map. And, to remove the data loss and the data deformation in Pro-Engineer, the product surface are delivered to the next process after it is changed to the 2 dimensional Z-map curves in CATIA. Finally, this paper suggests an algorithm to develop the automatic design program for the press layout which regenerates product shape surface from the previous process.

• Journal of the Korean Society for Precision Engineering
• /
• v.21 no.5
• /
• pp.131-141
• /
• 2004

In this study a 3-D automatic die design supporting system for a bonnet panel has been developed using Pro/ROGRAM of the widespread CAD software Pro/ENGINEER A standard drawing die was defined in terms of the punch profile, the die face geometry, and the blank sheet size. The strip layout of a trimming die was defined, in addition, in terms of the trimming line and the locations of scrap cutters. Necessary relations for each design step are formulated and rules for bottom-up type 3-D die design were set up for the automatic design of drawing and trimming dies of a bonnet. With the input geometric data of punch profile, die face, and blank sheet, this 3-D design supporting system could complete the basic design process, in case of the bonnet drawing die, in a time 78% shorter than that required by a typical 2-D CAD system. The new design system showed remarkable design efficiency also when it was applied to the case of redesign and modification of the previous standard output for a different car type.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.5
• /
• pp.572-579
• /
• 1988

In this paper, a system of automatic placement and routing for gate array layout design is proposed. In the placement stage, the circuit is partitioned and using the concept of min-cut slicing, and each partitioned module is placed, so that the routing density over the entire chip be uniformized and the total wiring length be minimized. In the global routing stage, the concept of the probabilistic routing density is introduced to unify the wiring congestions in each channel. In the detailed routing stage, the multi-terminal nets are partitioned into the two-terminal nets. The ordered channel graph is proposed which implies the vertical and the horizontal constranint graphs simultaneously. And using the ordered channel graph, the proposed routing algorithm assigns the signal nets to the tracks. Also the proposed placement and routing algorithms are implimented on IBM/PC-AT to construct PC-level gate array layout system.

• The KIPS Transactions:PartA
• /
• v.16A no.2
• /
• pp.101-112
• /
• 2009

Existing techniques for defragmentation of the file system need intensive disk operation for some periods at specific time such as disk defragmentation program. In this paper, for solving this problem, we design and implement the automatic and continuous defragmentation free system by distributing the disk operation. We propose the Automatic Layout Scoring(ALS) mechanism for measuring defragmentation degree and suggest the Lazy Copy mechanism that copies the defragmented data at idle time for scattering the disk operation. We search the defragmented file by Automatic Layout Scoring mechanism and then find for empty spaces for that searched file. After lazy copy of searched fils to empty space for preventing that file from being lost, the algorithm solves the defragmentation problem by updating the I-node of that file. We implement these algorithms in Linux and evaluate them for small and defragmented file to get the layout scoring. We outperform the Linux EXT2 file system by $2.4%{\sim}10.4%$ in layout scoring evaluation. And the performance of read and write for various file size is better than the EXT2 by $1%{\sim}8.5%$ for write performance and by $1.2%{\sim}7.5%$ for read performance. We suggest this system for solving the problem of defragmentation automatically without disturbing the I/O task and manual management.

• IE interfaces
• /
• v.12 no.1
• /
• pp.32-42
• /
• 1999

This paper proposes and implementation procedure for an automatic assembly system from a manual assembly and an evaluation method of implemented several automatic system alternatives using an AHP (Analytic Hierarchy Process) in a small-sized motor. First, the current product is redesigned for DFA (Design For Assembly) and assembly automation of motor, and then it is decided mechanisms of moving, magazining, feeding, composing of each part using main joining equipment and auxiliary equipment. Following the decided mechanism, the necessary assembly machines are selected or designed considering objectives and assembly conditions. Finally, the layout alternatives are completed for the automatic assembly system. According to the evaluation criteria which are established in advance, the automatic system alternatives are analyzed using AHP.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.15 no.10
• /
• pp.857-867
• /
• 1990

Sine CAM structure is regular structure as that of RAM of PLA, CAM generator program is easy to implement. This program outputs CAM layout in the form of CIF(Caltech Intermediate Format) and graphic display program is debugging or displaying CAM generator output, which are implemented on PC/AT with MS C(5.0) graphic library and C language. CIF parser is programmed with YACC(Yet Another Compiler Compiler) and LEX (Lexical Analyzer) in order to flat the CIF data. For the purposed of plotting the layout output using ROLAND XY plotter is developed. By combining these program described above, from CIF generation to layout plotting can be executed on pull-down menu according to user's option.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.5
• /
• pp.1240-1252
• /
• 1996

In this paper we propose a layout editor for the functional module generation in the Sea-of Gates(SOG) lay-out style. The proposed layout editor provides interactive was of designing a functional module to the designer so that the layout result is very satisfiable. Especially, the editor is independent on the shape of the basic cells in the gate array template, and provides semi-automatic layout methods as well as hand layout. It also has several special functions which are not able to find in other layout tools for the module generation, and hence the designer can generate modules very fast. The layout editors implemented in C language with X-win-dow Motif environment. When we compare our editor with the previous layout editor Seadali, the design time is reduced by a factor of two for several benchmark circuits.