• Transactions on Electrical and Electronic Materials
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• 제12권2호
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• pp.51-55
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• 2011

We investigated the etching characteristics of zinc oxide (ZnO) thin films deposited by the atomic layer deposition method. The gases of the inductively coupled plasma chemistry consisted of $Cl_2$, Ar, and $O_2$. The maximum etch rate was 40.3 nm/min at a gas flow ratio of $Cl_2$/Ar=15:5 sccm, radio-frequency power of 600 W, bias power of 200 W, and process pressure of 2 Pa. We also investigated the plasma induced damage in the etched ZnO thin films using X-ray diffraction (XRD), atomic force microscopy and photoluminescence (PL). A highly oriented (100) peak was present in the XRD spectroscopy of the ZnO samples. The full width at half maximum value of the ZnO sample etched using the $O_2/Cl_2$/Ar chemistry was higher than that of the as-deposited sample. The roughness of the ZnO thin films increased from 1.91 nm to 2.45 nm after etching in the $O_2/Cl_2$/Ar plasma chemistry. Also, we obtained a strong band edge emission at 380 nm. The intensities of the peaks in the PL spectra from the samples etched in all of the chemistries were increased. However, there was no deep level emission.

• 한국결정성장학회지
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• 제9권6호
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• pp.597-600
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• 1999

단결정규소 웨이퍼를 15% HF-에탄올 용액에서 양극 산화시켜 다공질규소를 얻는 과정에서 전류밀도와 에칭시간에 따라 굴절률이 주기적으로 변하는 다층의 다공질규소층(porous silicon multilayers)을 구현하였다. 그리고 다층의 다공질규소층(I), 다공질규소 발광층, 또 다른 다층의 다공질규소층(II)의 순으로 구성된 porous silicon microcavity(PSM)를 제작하고 그 물성을 조사하였다. PSM 상하에 위치한 다층의 다공질규소층의 단면을 AFM(Atomic Force Microscope)으로 조사한 결과 고굴 절률과 저굴절률이 주기적으로 교차하는 층이 균일하게 형성되었으며, 중앙의 다공질규소 발광층도 균일하게 나타났다. 다층의 다공질규소층 및 다공질규소 발광층의 두께를 각각 실효파장의 1/4배 및 2배가 되도록 하였을 때 특정파장의 필터로 쓰일 수 있는 브래그 반사경(Bragg reflector)의 특성이 나타났다. 또한 PSM의 발광 스펙트럼은 그 반치폭이 현저히 감소하고 발광의 세기가 크게 증가되는 경향을 보였다.

• ETRI Journal
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• 제38권4호
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• pp.675-684
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• 2016

This paper demonstrates the effect of fluoride-based plasma treatment on the performance of $Al_2O_3/AlGaN/GaN$ metal-insulator-semiconductor heterostructure field effect transistors (MISHFETs) with a T-shaped gate length of $0.20{\mu}m$. For the fabrication of the MISHFET, an $Al_2O_3$ layer as a gate dielectric was deposited using atomic layer deposition, which greatly decreases the gate leakage current, followed by the deposition of the silicon nitride layer. The silicon nitride layer on the gate foot region was then selectively removed through a reactive ion etching technique using $CF_4$ plasma. The etching process was continued for a longer period of time even after the complete removal of the silicon nitride layer to expose the $Al_2O_3$ gate dielectric layer to the plasma environment. The thickness of the $Al_2O_3$ gate dielectric layer was slowly reduced during the plasma exposure. Through this plasma treatment, the device exhibited a threshold voltage shift of 3.1 V in the positive direction, an increase of 50 mS/mm in trans conductance, a degraded off-state performance and a larger gate leakage current compared with that of the reference device without a plasma treatment.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.68-69
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• 2005

BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant. It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the self-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS), respectively. The removal rate of BTO thin film using the$ BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%. The sufficient within-wafer non-uniformity (WIWNU%)below 5% was obtained in each abrasive at all concentrations. The surface morphology of polished BTO thin film was investigated by atomic force microscopy (AFM).

• 한국재료학회지
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• 제24권12호
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• pp.682-688
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• 2014

Physical and chemical changes in a polished wafer and in $2.5{\mu}m$ & $4{\mu}m$ epitaxially grown Si layer wafers (Epilayer wafer) after surface treatment were investigated. We characterized the influence of surface treatment on wafer properties such as surface roughness and the chemical composition and bonds. After each surface treatment, the physical change of the wafer surface was evaluated by atomic force microscopy to confirm the surface morphology and roughness. In addition, chemical changes in the wafer surface were studied by X-ray photoemission spectroscopy measurement. Changes in the chemical composition were confirmed before and after the surface treatment. By combined analysis of the physical and chemical changes, we found that diluted hydrofluoric acid treatment is more effective than buffered oxide etching for $SiO_2$ removal in both polished and Epi-Layer wafers; however, the etch rate and the surface roughness in the given treatment are different among the polished $2.5{\mu}m$ and $4{\mu}m$ Epi-layer wafers in spite of the identical bulk structural properties of these wafers. This study therefore suggests that independent surface treatment optimization is required for each wafer type, $2.5{\mu}m$ and $4{\mu}m$, due to the meaningful differences in the initial surface chemical and physical properties.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2015년도 추계학술대회 논문집
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• pp.241-241
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• 2015

플라즈마 건식 식각 기술은 반도체 식각공정에서 효과적으로 이용되고 있으며, 반도체 소자의 크기가 줄어듬에 따라 미세하고 정확하게 식각 깊이를 제어 할 수 있는 원자층 식각기술 많은 관심을 받고 있다. 실리콘을 대체 할 수 있는 우수한 전기적 특성을 가진 III-V 화합물 반도체 재료인 InGaAs에 대한 원자층 식각을 통하여, 흡착가스에 대한 표면흡착 및 탈착가스에 대한 표면탈착 메커니즘을 고찰하였다. 또한, 성분 및 표면분석 장치를 이용하여 InGaAs 원자층 식각 특성에 대해 연구하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.239-240
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• 2008

As semiconductor devices are scaled down for better performance and more functionality, the Cu-based interconnects suffer from the increase of the resistivity of the Cu wires. The resistivity increase, which is attributed to the electron scattering from grain boundaries and interfaces, needs to be addressed in order to further scale down semiconductor devices [1]. The increase in the resistivity of the interconnect can be alleviated by increasing the grain size of electroplating (EP)-Cu or by modifying the Cu surface [1]. Another possible solution is to maximize the portion of the EP-Cu volume in the vias or damascene structures with the conformal diffusion barrier and seed layer by optimizing their deposition processes during Cu interconnect fabrication, which are currently ionized physical vapor deposition (IPVD)-based Ta/TaN bilayer and IPVD-Cu, respectively. The use of in-situ etching, during IPVD of the barrier or the seed layer, has been effective in enlarging the trench volume where the Cu is filled, resulting in improved reliability and performance of the Cu-based interconnect. However, the application of IPVD technology is expected to be limited eventually because of poor sidewall step coverage and the narrow top part of the damascene structures. Recently, Ru has been suggested as a diffusion barrier that is compatible with the direct plating of Cu [2-3]. A single-layer diffusion barrier for the direct plating of Cu is desirable to optimize the resistance of the Cu interconnects because it eliminates the Cu-seed layer. However, previous studies have shown that the Ru by itself is not a suitable diffusion barrier for Cu metallization [4-6]. Thus, the diffusion barrier performance of the Ru film should be improved in order for it to be successfully incorporated as a seed layer/barrier layer for the direct plating of Cu. The improvement of its barrier performance, by modifying the Ru microstructure from columnar to amorphous (by incorporating the N into Ru during PVD), has been previously reported [7]. Another approach for improving the barrier performance of the Ru film is to use Ru as a just seed layer and combine it with superior materials to function as a diffusion barrier against the Cu. A RulTaN bilayer prepared by PVD has recently been suggested as a seed layer/diffusion barrier for Cu. This bilayer was stable between the Cu and Si after annealing at $700^{\circ}C$ for I min [8]. Although these reports dealt with the possible applications of Ru for Cu metallization, cases where the Ru film was prepared by atomic layer deposition (ALD) have not been identified. These are important because of ALD's excellent conformality. In this study, a bilayer diffusion barrier of Ru/TaCN prepared by ALD was investigated. As the addition of the third element into the transition metal nitride disrupts the crystal lattice and leads to the formation of a stable ternary amorphous material, as indicated by Nicolet [9], ALD-TaCN is expected to improve the diffusion barrier performance of the ALD-Ru against Cu. Ru was deposited by a sequential supply of bis(ethylcyclopentadienyl)ruthenium [Ru$(EtCp)_2$] and $NH_3$plasma and TaCN by a sequential supply of $(NEt_2)_3Ta=Nbu^t$ (tert-butylimido-trisdiethylamido-tantalum, TBTDET) and $H_2$ plasma. Sheet resistance measurements, X-ray diffractometry (XRD), and Auger electron spectroscopy (AES) analysis showed that the bilayer diffusion barriers of ALD-Ru (12 nm)/ALD-TaCN (2 nm) and ALD-Ru (4nm)/ALD-TaCN (2 nm) prevented the Cu diffusion up to annealing temperatures of 600 and $550^{\circ}C$ for 30 min, respectively. This is found to be due to the excellent diffusion barrier performance of the ALD-TaCN film against the Cu, due to it having an amorphous structure. A 5-nm-thick ALD-TaCN film was even stable up to annealing at $650^{\circ}C$ between Cu and Si. Transmission electron microscopy (TEM) investigation combined with energy dispersive spectroscopy (EDS) analysis revealed that the ALD-Ru/ALD-TaCN diffusion barrier failed by the Cu diffusion through the bilayer into the Si substrate. This is due to the ALD-TaCN interlayer preventing the interfacial reaction between the Ru and Si.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.62-62
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• 2015

In this study, we study the effects of CF4 plasma treatment on the characteristics of enhancement mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs). The CF4 plasma is generated by inductively coupled plasma reactive ion etching (ICP-RIE) system. The CF4 gas is decomposed into fluorine ions by ICP-RIE and then fluorine ions will effect the AlGaN/GaN interface to inhibit the electron transport of two dimension electron gas (2DEG) and increase channel resistance. The CF4 plasma method neither like the recessed type which have to utilize Cl2/BCl3 to etch semiconductor layer nor ion implantation needed high power to implant ions into semiconductor. Both of techniques will cause semiconductor damage. In the experiment, the CF4 treatment time are 0, 50, 100, 150, 200 and 250 seconds. It was found that the devices treated 100 seconds showed best electric performance. In order to prove fluorine ions existing and CF4 plasma treatment not etch epitaxial layer, the secondary ion mass spectrometer confirmed fluorine ions truly existing in the sample which treatment time 100 seconds. Moreover, transmission electron microscopy showed that the sample treated time 100 seconds did not have etch phenomena. Atomic layer deposition is used to grow Al2O3 with thickness 10, 20, 30 and 40 nm. In electrical measurement, the device that deposited 20-nm-thickness Al2O3 showed excellent current ability, the forward saturation current of 210 mA/mm, transconductance (gm) of 44.1 mS/mm and threshold voltage of 2.28 V, ION/IOFF reach to 108. As IV concerning the breakdown voltage measurement, all kinds of samples can reach to 1450 V.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.28-28
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• 2009

Fabrications of antireflection structures on solar cell were investigated to trap the light and to improve quantum efficiency. Introductions of patterned substrate or textured layer for Si solar cell were performed to prevent reflectance and to increase the path length of incoming light. However, it is difficult to deposit conformally flat electrode on perpendicular plane. ZnO is II-VI compound semiconductor and well-known wide band-gap material. It has similar electrical and optical properties as ITO, but it is nontoxic and stable. In this study, Al-doped ZnO thin films are deposited as transparent electrode by atomic layer deposition method to coat on Si substrate with micro-scale structures. The deposited AZO layer is flatted on horizontal plane as well as perpendicular one with conformal 200 nm thickness. The carrier concentration, mobility and resistivity of deposited AZO thin film on glass substrate were measured $1.4\times10^{20}cm^{-3}$, $93.3cm^2/Vs$, $4.732\times10^{-4}{\Omega}cm$ with high transmittance over 80%. The AZO films were coated with polyimide and performed selective polyimide stripping on head of column by reactive ion etching to measure resistance along columns surface. Current between the micro-columns flows onto the perpendicular plane of deposited AZO film with low resistance.