• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.177.2-177
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• 2001

The asynchronous gyro outputs in the 3-axis navigation system are defined as each of gyros has its own output frequency. In this case, the navigation system has gyro outputs concurrently with the sensor mechanical frequency instead of the attitude frequency. So, there is an asynchronous error between gyro outputs and attitude calculation. In this paper, we analyze the gyro output error caused by the asynchronous gyro and present the high speed sampling technique and the extrapolation and interpolation of gyro outputs for synchronizing the gyro outputs.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.3
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• pp.591-597
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• 2009

The problem of controlling a finite-state asynchronous sequential machine is examined. The considered machine is governed by input/output control, where access to the state of the machine is not available. In particular, disturbance inputs can infiltrate into the asynchronous machine and provoke unauthorized state transitions. The control objective is to use output feedback to compensate the machine so that the closed-loop system drive the faulty asynchronous machine from a failed state to the original one. Necessary and sufficient condition for the existence of appropriate controllers are presented in a theoretical framework. As a case study, the closed-loop system of an asynchronous machine with the proposed control scheme is implemented in VHDL code.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.221-225
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• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• ETRI Journal
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• v.35 no.1
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• pp.35-40
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• 2013

Asynchronous ranging is one practical method to implement a locating system that provides accurate results. However, a locating system utilizing asynchronous ranging generates a large number of messages that cause transmission delays or failures and degrades the system performance. This paper proposes a novel approach for efficient congestion control in an asynchronous range-based locating system. The proposed method significantly reduces the number of messages generated during the reader discovery phase by eavesdropping on other transmissions and improves the efficiency of ranging by organizing the tags in a hierarchical fashion in the measurement phase. Our evaluation shows that the proposed method reduces the number of messages by 70% compared to the conventional method and significantly improves the success rate of ranging.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.4
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• pp.326-334
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• 1991

We propose an optical Asynchronous Transfer Mode(ATM) switching system using free-space optics and an output buffer memory. The distributor system in the switching fabric was analyzed using the Huygens-Fresnel principle and lens transformation. For monochromatic illumination, a pattern similar to the Fourier transform of the input distribution was observed across the output plane. A spatially broadened intensity distribution across the the output plane can be expected when the system is illminated with a partially coherent, quasimonochromatic beam. Spatially coherent pulses as short as 100fs can propagate through the distributor without severe spatial broadening.

• Journal of Electrical Engineering and Technology
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• v.2 no.3
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• pp.358-365
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• 2007

This paper deals with a novel solid state controller (NSSC) for parallel operated isolated asynchronous generators (IAG) feeding 3-phase 4-wire loads in constant power applications, such as uncontrolled pico hydro turbines. AC capacitor banks are used to meet the reactive power requirement of asynchronous generators. The proposed NSSC is realized using a set of IGBTs (Insulated gate bipolar junction transistors) based current controlled 4-leg voltage source converter (CC-VSC) and a DC chopper at its DC bus, which keeps the generated voltage and frequency constant in spite of changes in consumer loads. The complete system is modeled in MATLAB along with simulink and PSB (power system block set) toolboxes. The simulated results are presented to demonstrate the capability of isolated generating system consisting of NSSC and parallel operated asynchronous generators driven by uncontrolled pico hydro turbines and feeding 3-phase 4-wire loads.

• Journal of the Korean Institute of Intelligent Systems
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• v.25 no.2
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• pp.139-146
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• 2015

This paper presents the solution to model matching of switched asynchronous sequential machines by corrective control. We propose a model of switched asynchronous sequential machines, in which the system can have different dynamics of asynchronous machines governed by a pre-determined sequence of switching. The control objective is to derive a corrective control law so that the stable state behavior of the closed-loop system can match that of a prescribed model. A new skeleton matrix is defined to represent the reachability of the switched asynchronous machine, and a novel control scheme is presented that interweaves the switching signal and the corrective control procedure. A design algorithm for the proposed controller is illustrated in a case study.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.11
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• pp.1125-1131
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• 2011

This paper presents a control theoretic approach to realizing fault tolerance in asynchronous sequential circuits. The considered asynchronous circuit is assumed to work in space environment and is subject to faults caused by total ionizing dose (TID) effects. In our setting, TID effects cause permanent changes in state transition characteristics of the asynchronous circuit. Under a certain condition of reachability redundancy, it is possible to design a corrective controller so that the closed-loop system can maintain the normal behavior despite occurrences of TID faults. As a case study, the proposed control scheme is applied to an asynchronous arbiter implemented in FPGA.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.351-362
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• 2002

Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.2
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• pp.86-94
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• 2014

Optical packet switching (OPS) is being considered as one of the switching technologies for a future optical internet. For contention resolution in an optical packet switching (OPS) system, the wavelength dimension is generally used in combination with a fiber delay line (FDL) buffer. In this article, we propose a method to reduce the number of tunable wavelength converters (TWCs) by sharing TWCs for a cost-effective design of an asynchronous OPS system with a shared or an output FDL buffer. Asynchronous and variable-length packets are considered in the OPS system design. To investigate the number of TWCs needed for the OPS system, an algorithm is proposed, which searches for an available TWC and an unused internal wavelength, as well as an outgoing channel. This algorithm is applied to an OPS system with a shared or an output FDL buffer. Also, the number of internal wavelengths (i.e., the conversion range of the TWC) needed for an asynchronous OPS system is presented for cost reduction of the OPS system.