• Proceedings of the KIEE Conference
• /
• 2006.10d
• /
• pp.125-128
• /
• 2006

This paper presents a novel type soft switching PWM power frequency AC-AC converter using bidirectional active switches or single phase utility frequency AC-high frequency AC matrix converter. This converter can directly convert utility frequency AC (UFAC, 50Hz/60Hz) power to high frequency AC (HFAC) power ranging more than 20kHz up to 100kHz. A novel soft switching PWM prototype of high frequency multi-resonant PWM controlled UFAC-HFAC matrix converter using antiparallel one-chip reverse blocking IGBTs manufactured by IXYS corp. is based on the soft switching resonance with asymmetrical duty cycle PWM strategy. This single phase UFAC-HFAC matrix converter has some remarkable features as electrolytic capacitor DC busline linkless topology, unity power factor correction and sine-wave line current shaping, simple configuration with minimum circuit components, high efficiency and downsizing. This series load resonant UFAC-HFAC matrix converter, incorporating bidirectional active power switches is developed and implemented for high efficiency consumer induction heated food cooking appliances in home uses and business-uses. Its operating performances as soft switching operating ranges and high frequency effective power regulation characteristics are illustrated and discussed on the basis of simulation and experimental results.

• Journal of Power Electronics
• /
• v.17 no.1
• /
• pp.222-231
• /
• 2017

In this paper, a new architecture for a cost-effective power conditioning systems (PCS) using a single-sourced asymmetric cascaded H-bridge multilevel inverter (MLI) for photovoltaic (PV) applications is proposed. The asymmetric MLI topology has a reduced number of parts compared to the symmetrical type for the same number of voltage level. However, the modulation index threshold related to the drop in the number of levels of the inverter output is higher than that of the symmetrical MLI. This problem results in a modulation index limitation which is relatively higher than that of the symmetrical MLI. Hence, an extra voltage pre-regulator becomes a necessary component in the PCS under a wide operating bias variation. In addition to pre-stage voltage regulation for the constant MLI dc-links, another auxiliary pre-regulator should provide isolation and voltage balance among the multiple H-bridge cells in the asymmetrical MLI as well as the symmetrical ones. The proposed PCS uses a single-ended DC-DC converter topology with a coupled inductor and charge-pump circuit to satisfy all of the aforementioned requirements. Since the proposed integrated-type voltage pre-regulator circuit uses only a single MOSFET switch and a single magnetic component, the size and cost of the PCS is an optimal trade-off. In addition, the voltage balance between the separate H-bridge cells is automatically maintained by the number of turns in the coupled inductor transformer regardless of the duty cycle, which eliminates the need for an extra voltage regulator for the auxiliary H-bridge in MLIs. The voltage balance is also maintained under the discontinuous conduction mode (DCM). Thus, the PCS is also operational during light load conditions. The proposed architecture can apply the module-integrated converter (MIC) concept to perform distributed MPPT. The proposed architecture is analyzed and verified for a 7-level asymmetric MLI, using simulation results and a hardware implementation.

• The KIPS Transactions:PartA
• /
• v.18A no.4
• /
• pp.135-142
• /
• 2011

This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.