• The KIPS Transactions:PartA
• /
• v.14A no.1 s.105
• /
• pp.47-54
• /
• 2007

In this paper we present a translation lookaside buffer (TLB) system with low power consumption for imbedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the block buffer (tag buffer). Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism. The performance overhead of the proposed TLB is negligible compared with other hierarchical TLB structures. For example, the two-cycle overhead of the proposed TLB is only about 1%, as compared with 5% overhead for a filter (micro)-TLB and 14% overhead for a same structure without continuos accessing distinction algorithm. We show that the average hit ratios of the block buffers and the main banks of the proposed TLB are 95% and 5% respectively. Dynamic power is reduced by about 95% with respect to with a fully associative TLB, 90% with respect to a filter-TLB, and 40% relative to a same structure without continuos accessing distinction algorithm.

• Journal of KIISE:Computer Systems and Theory
• /
• v.37 no.5
• /
• pp.292-303
• /
• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.

• Journal of Korea Water Resources Association
• /
• v.31 no.1
• /
• pp.13-25
• /
• 1998

It is necessary to develop methodologies for the application of artificial neural network into hydrologic rainfall-runoff process, although there is so much applicability by using the functions of associative memory based on recognition for the relationships between causes and effects and the excellent fitting capacity for the nonlinear phenomenon. In this study, some problems are presented in the application procedures of artificial neural networks and the simulation of runoff hydrograph experiences are reviewed with nonlinear functional approximator by artificial neural network for rainfall-runoff relationships in a watershed. which is regarded as hydrdologic black box model. The neural network models are constructed by organizing input and output patterns with the deserved rainfall and runoff data in Pyoungchang river basin under the assumption that the rainfall data is the input pattern and runoff hydrograph is the output patterns. Analyzed with the results. it is possible to simulate the runoff hydrograph with processing element of artificial neural network with any hydrologic concepts and the weight among processing elements are well-adapted as model parameters with the assumed model structure during learning process. Based upon these results. it is expected that neural network theory can be utilized as an efficient approach to simulate runoff hydrograph and identify the relationship between rainfall and runoff as hydrosystems which is necessary to develop and manage water resources.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.11
• /
• pp.24-32
• /
• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of Biosystems Engineering
• /
• v.29 no.4
• /
• pp.341-346
• /
• 2004

Recent livestock people concern not only increase of production, but also superior quality of animal-breeding environment. So far, the optimization of the breeding and air environment has been focused on the production increase. In the very near future, the optimization will be emphasized on the environment for the animal welfare and health. Especially, cattle farming demands the precision livestock farming and special attention has to be given to the management of feeding, animal health and fertility. The management of individual animal is the first step for precision livestock farming and animal welfare, and recognizing each individual is important for that. Though electronic identification of a cattle such as RFID(Radio Frequency Identification) has many advantages, RFID implementations practically involve several problems such as the reading speed and distance. In that sense, computer vision might be more effective than RFID for the identification of an individual animal. The researches on the identification of cattle via image processing were mostly performed with the cows having black-white patterns of the Holstein. But, the native Korean and Japanese cattle do not have any definite pattern on the body. The purpose of this research is to identify the Japanese black cattle that does not have a body pattern using computer vision technology and neural network algorithm. Twelve heads of Japanese black cattle have been tested to verify the proposed scheme. The values of input parameters were specified and then computed using the face images of cattle. The images of cattle faces were trained using associate neural network algorithm, and the algorithm was verified by the face images that were transformed using brightness, distortion, and noise factors. As a result, there was difference due to transform ratio of the brightness, distortion, and noise. And, the proposed algorithm could identify 100% in the range from -3 to +3 degrees of the brightness, from -2 to +4 degrees of the distortion, and from 0% to 60% of the noise transformed images. It is concluded that our system can not be applied in real time recognition of the moving cows, but can be used for the cattle being at a standstill.