• Tribology and Lubricants
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• v.30 no.3
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• pp.139-145
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• 2014

Nowadays, most micro-patterns are manufactured during flow line production. However, a conventional rotary chemical mechanical polishing (CMP) system has a limited throughput for the fabrication of large and flexible electronics. To overcome this problem, we propose a novel linear roll-CMP system for the planarization of large-area electronics. In this paper, we present a statistical analysis on the linear roll-CMP process of copper-clad laminate (CCL) to determine the impacts of process parameters on the material removal rate (MRR) and its non-uniformity (NU). In the linear roll-CMP process, process parameters such as the slurry flow rate, roll speed, table feed rate, and down force affect the MRR and NU. To determine the polishing characteristics of roll-CMP, we use Taguchi's orthogonal array L16 (44) for the experimental design and F-values obtained by the analysis of variance (ANOVA). We investigate the signal-to-noise (S/N) ratio to identify the prominent control parameters. The "higher is better" for the MRR and "lower is better" for the NU were selected for obtaining optimum CMP performance characteristics. The experimental and statistical results indicate that the down force and roll speed mainly affect the MRR and the down force and table feed rate determine the NU in the linear roll-CMP process. However, over 186.3 N of down force deteriorates the NU because of the bending of substrate. Roll speed has little relationship to the NU and the table feed rate does not impact on the MRR. This study provides information on the design parameter of roll-CMP machine and process optimization.

• Journal of Biosystems Engineering
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• v.31 no.1 s.114
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• pp.33-38
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• 2006

This work was conducted to find the operating characteristics of an efficient wet grinding system designed to obtain fine rice husk ash powder. Once the rice husk was combusted and the thermal energy was recovered from the furnace, the ash was fed and pulverized in the grinding system resulting a fine powder to be used as a supplementary adding material to the portland cement. Grinding time (15, 30, 45 min), impeller speed (250, 500, 750 rpm), and mixed ratio (6.7, 8.4, 11.l, 20.9) were three operating factors examined for the performance of a wet-type stirred ball mill grinding system. For the operating conditions employed, mean diameter of fine ash powder, specific energy input, and grinding energy efficiency were in the range of $2.83{\sim}9.58{\mu}m,\;0.5{\sim}6.73kWh/kg,\;and\;0.51{\sim}3.27m^2/Wh$, respectively. With the wet-type stirred ball mill grinding system used in this study, the grinding energy efficiency decreased with the increase in total grinding time, impeller speed, and mixed ratio. The difference in specific surface area of powder linearly increased with logarithm in total number of impeller revolution and the grinding energy efficiency linearly decreased. Grinding time of 45 min, impeller speed of 500 rpm, and mixed ratio of 6.7 were chosen as the best operating condition. At this condition, mean particle diameter of the fine ash, grinding energy efficiency, grinding throughput, and specific energy input were $2.84{\mu}m,\;2.28m^2/Wh,\;0.17kg/h$, and 2.03kWh/kg, respectively. Wet fine grinding which generates no fly dust causing pollution and makes continuous operation easy, is appeared to be a promising solution to the automatization of rice husk ash grinding process.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.1
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• pp.10-18
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• 2007

Mobile communication devices such as PDAs, cellular phones, etc., need to perform several kinds of computation-intensive functions including H.264 encoding/decoding and 3D graphics processing. In this paper, new reconfigurable architecture is described, which can perform either motion estimation for H.264 or rendering for 3D graphics. The proposed motion estimation techniques use new efficient SAD computation ordering, DAU, and FDVS algorithms. The new approach can reduce the computation by 70% on the average than that of JM 8.2, without affecting the quality. In 3D rendering, midline traversal algorithm is used for parallel processing to increase throughput. Memories are partitioned into 8 blocks so that 2.4Mbits (47%) of memory is shared and selective power shutdown is possible during motion estimation and 3D graphics rendering. Processing elements are also shared to further reduce the chip area by 7%.

• Journal of KIISE
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• v.41 no.9
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• pp.605-610
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• 2014

Now, virtualization is no more emerging research area, and we can easily find its application in our circumstance. Nevertheless, I/O workloads are reluctant to be applied in virtual environment since they still suffer from unacceptable performance degradation due to virtualization latency. Many previous papers identified that virtual I/O overhead is mainly caused by exits and redundant I/O stack, and proposed several techniques to reduce them. However, they still have some limitations. In this paper, we introduce a novel I/O virtualization framework which improves I/O performance by exploiting multicore architecture. We applied our framework to the virtual network, and it improves TCP throughput up to 169%, and decreases UDP latency up to 38% on the network with the 10Gbps NIC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

• Journal of Navigation and Port Research
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• v.32 no.8
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• pp.653-658
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• 2008

The demand of international intermodal transportation is continuously increasing in accordance with a changing environment on international logistics, Under this circumstance, the Sea&Air intermodal transportation, combined by sea-based and air-based transport, has a potential growth in the future. After analyzing routes for Origin/Destination and implementing portfolio analysis, finally, this research aims to propose alternatives to create additional customers(or cargoes) for the Sea&Air transport. As a result of the analyses, China appeared to be a major customer of the Sea&Air transport in Korea because some of the Chinese areas - i.e. Qingdao, Shanghai, Weihai and Yantai - account for 88.1% of the total throughput. In general, this indicates that it would be more efficient to establish specific strategies targeting those major areas. Excluding the four areas, most of the other area, have much less demands and are relatively unstable. The demands, growth rates and market shares especially in Vladivostok, Dandong and Tianjinxingang are on the decrease, and therefore, stable strategies seems to be appropriate than aggressive strategies for these areas.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1495-1507
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• 1997

Among a number of approaches to text compression, adaptive dictionary schemes based on a sliding window have been very frequently used due to their high performance. The LZ77 algorithm is the most efficient algorithm which implements such adaptive schemes for the practical use of text compression. This paperpresents a VLSI architecture designed for processing the LZ77 algorithm in parallel. Compared with the other VLSI architectures developed so far, the proposed architecture provides the more viable solution to high performance with regard to its throughput, efficient implementation of the VLSI systolic arrays, and hardware scalability. Indeed, without being affected by the size of the sliding window, our system has the complexity of O(N) for both the compression and decompression and also requires small wafer area, where N is the size of the input text.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.7
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• pp.653-660
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• 2013

This paper deals with the problem of unfairness among uplink TCP (Transmission Control Protocol) flows associated with frame aggregation employed in IEEE 802.11n WLANs (Wireless Local Area Networks). When multiple stations have uplink TCP flows and transmit TCP data packets to an AP (Access Point), the AP has to compete for channel access with stations for the transmission of TCP ACK (acknowledgement) packets to the stations. Due to this contention-based channel access, TCP ACKs tend to be accumulated in the AP's downlink buffer. We show that the frame aggregation in the MAC (Medium Access Control) layer increases TCP ACK losses in the AP and leads to the serious unfair operation of TCP congestion control. To resolve this problem, we propose the TAC (TCP ACK Compression) mechanism operating at the top of the AP's interface queue. By exploiting the properties of cumulative TCP ACK and frame aggregation, TAC serves only the representative TCP ACK without serving redundant TCP ACKs. Therefore, TAC reduces queue occupancy and prevents ACK losses due to buffer overflow, which significantly contributes to fairness among uplink TCP flows. Also, TAC enhances the channel efficiency by not transmitting unnecessary TCP ACKs. The simulation results show that TAC tightly assures fairness under various network conditions while increasing the aggregate throughput, compared to the existing schemes.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.145-151
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• 2004

For wide-band spread spectrum communication systems such as IMT-2000, a digital matched filter is a key device for rapid spreading code synchronization. Although a digital matched filter can be implemented easily, large power consumption at the higher chip rate and large summation delay of longer chip length are the bottleneck of practical use. In this paper, we propose a optimized partial correlation digital matched filter structure which can be constructed of the so-called generalized hierarchical Golay sequence. a partial correlation structure can reduce the number of correlators, but enlarge the size of flip-flops. In this paper, The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. A proposed digital matched filter reduce the size of flip-flops by rounding method. and it reduces about 45 percentages of power dissipation and chip area as compared with digital matched filter which is not rounded. rounding. The proposed architecture was verified by using Xilinx FPGA.

• Journal of Navigation and Port Research
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• v.28 no.3
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• pp.177-184
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• 2004

The purpose of this study is to identify and evaluate the competitiveness of container ports in ASEAN(Association of Southeast Asian Nations) and Korea, which plays a leading role in basing the hub of international logistics strategies at the onset of the 21st century. Its ultimate purpose is to consider the relevant policy-making by comparing the competitiveness of ASEAN and Korea's container ports. This paper adopted the HFP method, which is an empirical analysis that evaluated the port competitiveness by quantifying it a, a qualitative attribute in the aforementioned area, where both ASEAN and Korea vie with each other for increasing container throughput. The results of this study showed that Singapore ranked the first in the subject of study in view of the competitiveness, followed by Busan(2) and Manila(2) as a leading group of the relevant ports in international logistics strategies. This analytic evaluation contributes to the empirical approach applied to policy-making by the HFP method, which is the newest research technique in social science through the comparative study of port competitiveness between ASEAN and Korea.