• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.45-53
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) encoding. Previous CAVLC architectures search all of the coefficients to find statistic characteristics in a block. However, it is unnecessary information that zero coefficients following the last position of a non-zero coefficient when CAVLC encodes residual coefficients. In order to reduce this unnecessary operation, we propose two techniques, which detect the first and last position of non-zero coefficients and arrange non-zero coefficients sequentially. By adopting these two techniques, the required processing time was reduced about 23% compared with previous architecture. It was designed in a hardware description language and total logic gate count is 16.3k using 0.18um standard cell library Simulation results show that our design is capable of real-time processing for $1920{\times}1088\;30fps$ videos at 81MHz.

• Journal of Information Technology and Architecture
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• v.9 no.3
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• pp.243-251
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• 2012

This paper presents the Conceptual Models of the Mission Space-Korea (CMMS-K), which is an ontology-based conceptual modeling framework of the mission space. Through modeling and simulating military trainings, we can reduce the cost of actual military trainings in terms of time, space, and supplies. CMMS-K is being developed to improve the interoperability and reusability of defense models and simulations. CMMS-K reflects the needs and characteristics of Korean military while referring to existing military conceptual modeling frameworks. The main components of CMMS-K contain domain ontologies, a mission space model description language, a mission space modeling tool, and a CMMS-K management system. CMMS-K domain ontologies consist of entity and task ontologies. In this paper, the CMMS-K domain ontologies are described in detail and the feasibility of the proposed method is discussed with a case study.

• Journal of Korea Multimedia Society
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• v.7 no.5
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• pp.721-736
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• 2004

Because of increasing the notebook computer and PDA, users' requirement with respect to mobility is growing more and more. However, current IP protocol is not changed IP address and can not deliver IP packets on new location of host in case moving another network. To solve this problem, the IETF has proposed mobile IP. Today users want to be provided suitable QoS in the internet since demand of services is variety. The policy-based network management is method which can solve various problems of QoS, security, and complication of management in IP networks. This paper presents the network topology constitution, operation procedure and architecture of policy-based network management for providing internet DiffServ on mobile IP environment. In this paper we propose policy classes of policy-based DiffServ network management on mobile environment and create policy scenarios using the proposed policy description language to represent the policy classes. Finally, we implemented a policy-based DiffServ network management system on mobile IP environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1064-1073
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• 2002

In this paper, we design and implement the Wireless Transaction Protocol (WTP) proposed by the Wireless Application Protocol (WAP) forum using a protocol development tool, SDL Development Tool (SDT). And we conduct a comparative performance evaluation of the WTP implementation with other three implementations that are based on different implementation models respectively: the server model, the coroutine model, and the activity-thread model. To implement WTP, we first use Unified Modeling Language (UML) for analyzing the protocol requirement and defining the protocol engine architecture. Next, we use Software Development Language (SDL) to design the protocol engine in details and then generate the WTP implementation automatically with the aid of SDT The code size of the WTP implementation generated by SDT is 62% larger than the other three implementations. However, its throughput and system response time for transaction processing is almost equal to the other three implementations when the number of concurrent clients is less than 3,000. If more than 5,000 concurrent clients tries, the transaction success rate abruptly decreases to 10% and system response time increases to 1,500㎳, due to the increased protocol processing time. But, it comes from the fact that the load overwhelms the capacity of the PC resource used in this experimentation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.61-68
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• 2008

In this paper, we propose an efficient hardware architecture and algorithm to increase an encoding process rate and implement a hardware for CABAC (Context Adaptive Binary Arithmetic Coding) which is used with one of the entropy coding ways for the latest video compression technique, H.264/AVC (Advanced Video Coding). CABAC typically provides a better high compression performance maximum 15% compared with CAVLC. However, the complexity of operation of CABAC is significantly higher than the CAVLC. Because of complicated data dependency during the encoding process, the complexity of operation is higher. Therefore, various architectures were proposed to reduce an amount of operation. However, they have still latency on account of complicated data dependency. The proposed architecture has two techniques to implement efficient pipeline architecture. The one is quick calculation of 7, 8th bits used to calculate a probability is the first step in Binary arithmetic coding. The other is one step reduced pipeline arcbitecture when the type of the encoded symbols is MPS. By adopting these two techniques, the required processing time was reduced about 27-29% compared with previous architectures. It is designed in a hardware description language and total logic gate count is 19K using 0.18um standard cell library.

• The KIPS Transactions:PartD
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• v.13D no.3 s.106
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• pp.383-390
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• 2006

Product-line engineering is a dreaming goal in software engineering research. Unfortunately, the current underlying technologies do not seem to be still not much matured enough to make it viable in the industry. Based on our experiences in working on mobile telephony systems over 3 years, now we are in the course of developing an approach to product-line engineering for mobile telephony system software. In this paper, the experiences are shared together with our research motivation and idea. Consequently, we propose an approach to building and maintaining telephony application logics from the perspective of scenes. As a Domain-Specific Language(DSL), Menu Navigation Viewpoint(MNV) DSL is designed to deal with the problem domain of telephony applications. The functional requirements on how a set of telephony application logics are configured can be so various depending on manufacturer, product concept, service carrier, and so on. However, there is a commonality that all of the currently used telephony application logics can be generally described from the point of user's view, with a set of functional features that can be combinatorially synthesized from typical telephony services(i.e. voice/video telephony, CBS/SMS/MMS, address book, data connection, camera/multimedia, web browsing, etc.), and their possible connectivity. MNV DSL description acts as a backbone software architecture based on which the other types of telephony application logics are placed and aligned to work together globally.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.283-289
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• 2005

In this paper, we propose two efficient symbol detection algorithms for space-frequency OFDM (SF-OFDM) transmit diversity scheme. When the number of sub-carriers in SF-OFBM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithms eliminate this interference in a parallel or sequential manlier and achieve a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithms is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithms achieve the gain improvement of about 3 dB. The symbol detectors with the proposed algorithms are designed in a hardware description language and synthesized to gate-level circuits with the $0.18{\mu}m$ 1.8V CMOS standard cell library. With the division-free architecture, the proposed SF-OFDM-PIC and SF-OFDM-SIC symbol detectors can be implemented using 140k and 129k logic gates, respectively.

• Journal of Internet of Things and Convergence
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• v.6 no.1
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• pp.97-102
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• 2020

Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.4
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• pp.321-328
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• 2008

In this paper, we propose the hardware architecture of two-dimensional discrete wavelet transform (2D DWT) and quantization for using JPEG2000. Color 2-D DWT processor is proposed that is to apply to JPEG 2000 Hard-wired Encoder. JPEG 2000 DWT processor uses the Daubechies' (9,7) bi-orthogonal filter, and we design by minimizing error of the DWT transformer by ${\pm}1$ LSB during compression and decompression. We designed the DWT filters that using by using shift and adder structure instead of multiplier structure which raise the hardware complexity. It is improve the operation speed of filters and reduce the hardware complexity. The proposed system is designed by the hardware description language Verilog-HDL and verified by Synopsys Design Analyzer using TSMC 0.25${\mu}m$ ASIC library.