• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.3
• /
• pp.333-340
• /
• 2017

In this paper, we describe HW/SW co-optimizations for reconfigurable application specific instruction-set processors (ASIPs). Based on our previous very long instruction word (VLIW) ASIP, the proposed framework realizes various forward error-correction (FEC) algorithms for wireless communication systems. In order to enhance the energy efficiency, we newly introduce several design methodologies including high-radix algorithms, task-level out-of-order executions, and intensive resource allocations with loop-level rescheduling. The case study on the radix-4 turbo decoding shows that the proposed techniques improve the energy efficiency by 3.7 times compared to the previous architecture.

• Proceedings of the Korean Society for Bioinformatics Conference
• /
• 2005.09a
• /
• pp.10-14
• /
• 2005

In this paper, we highlight the development of a web application system. Its main objective is to provide pathway visualization functionalities for inter-cytokine relationships, as well as for other types of relationships, with a specific cytokine(s) of interest. A natural language processor is first used to extract information from a certain web page that concerns the cytokine(s) of interest. The results obtained are then further processed and then displayed graphically to the user. The system displays how the cytokine(s) of interest interacts with other cytokines and cells. Useful information such as the type of reaction and catalyst involved, if any, are also displayed. In addition, the system also offers functionalities for graphical manipulations of the visualized pathways. The system has been shown to provide better overview, and hence, improved learning to readers who are new to this field by virtue of accurate inputs obtained from the natural language processing module.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 1995.10a
• /
• pp.1009-1012
• /
• 1995

This paper presents an example of the development of motor drives for machine tools. Machine tools need motor drives with high control precision and performance. We developed a motor drive system that meets these requirements. The converter, the one component of drive system, adopts modular structure and high DC-link voltage. The drive which consists rest part of drive system is developed based on TMS320C32 DSP and state-of-the-art circuit technology. In this paper each developed parts are described in terms of its structure, specification and features.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.32B no.1
• /
• pp.96-102
• /
• 1995

This paper presents the VHSIC Hardware Description Language(VHDL) implementation of the Fixed Point Covariance Lattice(FLAT) algorithm for an Linear Predictive Coding(LPC) analysis and its related algorithms, such as the forth order high pass Infinite Impulse Response(IIR) filter, covariance matrix calculation, and Spectral Smoothing Technique(SST) in the Vector Sum Exited Linear Predictive(VSELP) speech coder that has been Selected as the standard speech coder for the North America and Japanese digital cellular. Existing Digital Signal Processor(DSP) chips used in digital cellular phones are derived from general purpose DSP chips, and thus, these DSP chips may not be optimal and effective architectures are to be designed for the above mentioned algorithms. Then we implemented the VHDL code based on the C code, Finally, we verified that VHDL results are the same as C code results for real speech data. The implemented VHDL code can be used for performing logic synthesis and for designing an LPC Application Specific Integrated Circuit(ASOC) chip and DsP chips. We first developed the C language code to investigate the correctness of algorithms and to compare C code results with VHDL code results block by block.

• IEIE Transactions on Smart Processing and Computing
• /
• v.6 no.4
• /
• pp.292-298
• /
• 2017

The complexity of image compression algorithms has increased in order to improve image compression efficiency. One way to resolve high computational complexity is parallel processing. However, entropy coding, which is lossless compression, does not fit into the parallel processing form because of the correlation between consecutive symbols. This paper proposes a new application-specific instruction set processor (ASIP) platform by adding new context-adaptive binary arithmetic coding (CABAC) instructions to the existing platform to quickly process a variety of entropy coding. The newly added instructions work without conflicts with all other existing instructions of the platform, providing the flexibility to handle many coding standards with fast processing speeds. CABAC software is implemented for High Efficiency Video Coding (HEVC) and the performance of the proposed ASIP platform was verified with a field programmable gate array simulation.

• Proceedings of the Korea Society for Simulation Conference
• /
• 2002.11a
• /
• pp.73-77
• /
• 2002

이 논문은 빠른 ASIP(application specific instruction processor) 시뮬레이션을 위한 재적응성을 가진 컴파일드 시뮬레이션 기법에 대해 이야기 한다. 다양한 응용분야에서의 설계 요구사항을 충족시키는 ASIP의 빠른 개발을 위해서, 건전한 설계 방법론 및 고성능의 시뮬레이터가 필요하다. 본 논문에서는 HiX$R^2$라는 ADL(architecture description language)을 이용하여 인스트럭션 수준에서 컴파일드 시뮬레이터를 자동 생성하였다. 컴파일드 시뮬레이션은 시뮬레이션 수행 시 반복되는 인스트럭션 페칭 및 디코딩 부분을 시뮬레이션 런-타임 이전에 미리 수행함으로서 일반적으로 사용되는 인터프리티브 시뮬레이션에 비하여 큰 성능향상을 얻을 수 있다. HiX$R^2$에 기반 한 컴파일드 시뮬레이션은 ARM9 프로세서와 CalmRISC32 프로세서 예제들로 수행하였고, 결과로서 인터프리티브 방식에 비해 150배 이상의 성능향상이 있었다.

• Information and Communications Magazine
• /
• v.25 no.12
• /
• pp.10-18
• /
• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• Proceedings of the Korea Society for Simulation Conference
• /
• 2003.06a
• /
• pp.79-84
• /
• 2003

이 논문은 빠른 ASIP(application specific instruction processor) 평가를 위한 재적응성을 가진 컴파일러/시뮬레이터 환경에 대해 이야기한다. ASIP의 성능은 하드웨어 구조뿐만 아니라, 수행되는 응용 소프트웨어에 영향을 받기 때문에, 높은 성능의 ASIP 개발을 위해서는 컴파일러 및 시뮬레이터의 개발이 선행되어야 한다. 그러나 다양한 ASIP 구조에 따라 적합한 고성능의 컴파일러/시뮬레이터를 만드는 일은 매우 시간 소모적인 일이 될 뿐만 아니라, 오류가 발생하기도 쉽다. 본 논문에서는 HiXR2라는 ADL(architecture description language)을 이용하여 명령어 구조를 기술하고 이를 바탕으로 컴파일러와 시뮬레이터를 자동 생성하였다. HiXR2의 재적응성 및 생성된 컴파일러/시뮬레이터의 정확성을 검증하기 위하여 ARM9 프로세서와 CalmRISC32 프로세서 구조를 각각 기술하고, 각각에 대하여 응용프로그램 코드를 컴파일 및 시뮬레이션 하는 예제를 보였다.

• Journal of the Korea Society for Simulation
• /
• v.12 no.2
• /
• pp.45-53
• /
• 2003

This paper presents a retargetable compiled assembly simulation technique for fast ASIP(application specific instruction processor) simulation. Development of ASIP which satisfies design requirements in various fields of applications such as telecommunication, wireless network, etc. needs formal design methodology and high-performance relevant software environments such as compiler and simulator In this paper, we employ the architecture description language(ADL) named ${HiXR}^2$ to automatically synthesize an instruction-level compiled assembly simulator. A compiled simulation has benefit of time efficiency to interpretive one because it performs instruction fetching and decoding at compile time. Especially, in case of assembly simulation, instruction decoding is usually a time-consuming job(string operation), so the compiled simulation of assembly simulation is more efficient than that of binary simulation. Performance improvement of the compiled assembly simulation based on ${HiXR}^2$ is exemplified with an ARM9 architecture and a CalmRISC32 architecture. As a result, the compiled simulation is about 150 times faster than interpretive one.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.62 no.1
• /
• pp.127-132
• /
• 2013

In this paper, we design the physical layer of Guardian modem for wireless public networks. The physical layer is composed of a dual-band RF (Radio Frequency) transceiver and a baseband-processor with quasi-orthogonal codes. The 2.4/5GHz dual-band RF transceiver can overcome the communication difficulty of dense 2.4GHz band for wireless public environment. Also the quasi-orthogonal code can reduce the required ASIC (Application Specific Integrated Circuit) design area. Finally, we analyze the performance of the developed system in viewpoint of data rate, BER (Bit Error Rate), PER (Packet Error Rate). Moreover we verify the performance of the dual-band RF communication.