• Korean Journal of Soil Science and Fertilizer
• /
• v.32 no.2
• /
• pp.115-122
• /
• 1999

Investigation of nutrient movement in soil and soil water is necessary to clarify water purification functions and nutrient circulation within a forest ecosystem. In this study, seasonal changes in the nutrient content of soil and soil water was investigated in Korean white pine(Pinus koraiensis) and Japanese larch(Larix leptolepis) forest applied urea ($150kg\;ha^{-1}$). Soil pH was decreased rapidly in Japanese larch plot for a long period. On the other hand, soil pH was increased slightly in Korean white pine plot. T-C and T-N content were increased in both plots. In Japanes larch plot, exchangeable Ca and Mg contents were decreased remarkably than those in korean white pine plot while exchangeable K was increased rapidly after application. The effect of urea application on exchangeable K was not obvious compared to other cations. The pH, Ca, $NH_4-N$, $NO_3-N$, $SO_4-S$ and Cl concentrations in the sampled soil water at surface soil were increased only temporarily after fertilization, with the only exception of the decrease in pH of the soil water in Japanese larch plot. On the other hand, the peak value of K, Mg concentrations in the soil water was shown between 2 and 5 months after fertilization. The concentrations of Ca, $NO_3-N$, $SO_4-S$ and Cl returned to the values found before fertilization after about 1 month. Those of K, Mg, and $NO_3-N$ after 6-12 months.

• ETRI Journal
• /
• v.26 no.6
• /
• pp.583-588
• /
• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• Bulletin of the Korean Chemical Society
• /
• v.32 no.6
• /
• pp.1897-1901
• /
• 2011

This report shows the rates of solvolyses for phenyl methanesulfonyl chloride ($C_6H_5CH_2SO_2Cl$, I) in ethanol, methanol, and aqueous binary mixtures incorporating ethanol, methanol, acetone, 2,2,2-trifluroethanol (TFE) and 1,1,1,3,3,3-hexafluoro-2-propanol (HFIP) are reported. Three representative solvents, studies were made at several temperatures and activation parameters were determined. The thirty kinds of solvents gave a reasonably precise extended Grunwald-Winstein plot, coefficient (R) of 0.954. The sensitivity values (l = 0.61 and m = 0.34, l/m = 1.8) of phenyl methanesulfonyl chloride (I) were smaller than those obtained for benzenesulfonyl chloride ($C_6H_5SO_2Cl$, II; l = 1.01 and m = 0.61) and 2-propanesulfonyl chloride ($(CH_3)_2CHSO_2Cl$, III; l = 1.28 and m = 0.64). As with the two previously studied solvolyses, an $S_N2$ pathway with somewhat ionization reaction is proposed for the solvolyses of I. The activation parameters, ${\Delta}H^{\neq}$ and ${\Delta}S^{\neq}$, were determined and they are also in line with values expected for a bimolecular reaction mechanism. The kinetic solvent isotope effect of 2.34 in $CH_3OH/CH_3OD$ is in accord with a bimolecular mechanism, probably assisted by general-base catalysis.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.48 no.6
• /
• pp.489-493
• /
• 1999

In this paper, an analysis of microstrip-slotline transition is performed using a 3D vector Finite Element Method(FEM). Artificial anistropic absorber technique is employed to implement an matching boundary condition in FEM. On the base of the analysis, power divider/combiner is designed. The structure of the power combiner already developed are Branch-line coupler, Rat-race coupler, Wilkinson coupler, Lange coupler, etc. Which are all planar, If the frequency goes up, the coupling efficiency of these planar couplers is decreased on account of skin loss. Especially, in millimeter-wave band, the efficiency of more than two ways combiner is radically reduced, so that application in power amplifier circuit is almost impossible, Microstrip-slotline transition structure is a power combining technique integrated into wave-guide, so that the loss is small and the efficiency is high. Theoretically, we can mount several transistors into the power-combiner. This makes it possible to develop a high power amplifier. The numerically calculated performances of the device that is, we believe, the best are compared to the experimental results in Ka-Band(26.5GHz-40GHz).

• Journal of Korean Society for Quality Management
• /
• v.30 no.1
• /
• pp.74-96
• /
• 2002

The objectives of this study is to suggest the rectifying sampling inspection plan considering quality cost. Limiting quality level(LQL) plans(also called LTPD plans) and outgoing quality(OQ) plans are considered. The Hald's linear cost model is discussed with and without a beta prior for the distribution of the fraction of nonconforming items in a lot. It is assumed that the sampling inspection is error free. We consider the design of reliability acceptance sampling plan (RASP) for failure rate level qualification at selected confidence level. The lifetime distribution of products is assumed to be exponential. MIL-STD-690C and K C 6032 standards provide this procedures. But these procedures have some questions to apply in the field. The cost of test and confidence level(1-$\beta$ risk) are the problem between supplier and user. So, we suggest that the optimal life test sampling inspection plans using simple linear cost model considering product cost, capability of environment chamber, environmental test cost, and etc. Especially, we consider a reliability of lots that contain some nonconforming items. In this case we assumed that a nonconforming item fail after environmental life test. Finally, we develope the algorithm of the optimal sampling inspection plan based on minimum costs for rectifying inspection and RASP. And computer application programs are developed So, it is shown how the desired sampling plan can be easily found.

• Transactions of the Korean Society of Machine Tool Engineers
• /
• v.14 no.1
• /
• pp.81-88
• /
• 2005

There have been many studies on generation equipment and plant piping, but there is no significant study result on the heat transportation pipe. As such, this study established basic theory on the compensated method among buried pipe for regional heating, and further obtained the following results by applying the conditions of AGFW and NCHPP respectively in calculation of friction and maximum installation distance for the buried pipe. Friction coefficient according to the types and physical properties of soil, friction and maximum installation distance were compared to set the application value of friction coefficient according to the location of works. Calculation formula of clay load to be applied for calculation of friction was introduced to the formula of AGFW and the formula of NCHPP that has been used in Nowon district since 1997 to determine the difference and applicability. $120^{\circ}C$ and $95^{\circ}C$ were applied in temperature difference for expansion volume to compare the arm length at the curve pipe so thai it can be reflected in the design in the future. Maximum installation distance according to thickness of pipe was compared to present the necessity of unified specification so that same kinds of pipe materials can be used for same kinds of works.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.10a
• /
• pp.719-721
• /
• 2013

A thinning stage of fingerprint algorithm occupies 39% cycle of microprocessor system for identification processing of image from fingerprint sensor. Hardware block processing is more effective than software one in speed and power consumption, because a thinning algorithm is iteration of simple instructions without a transcendental function. This paper describes an effective hardware scheme for thinning stage processing using Verilog-HDL in $64{\times}64$ Pixel Array. The hardware scheme is designed and simulated in RTL. The logic is also synthesized by XST in FPGA environment and tested. Experimental results show the performance of the proposed scheme and possibility of application for a soft microprocessor and thinning processor embedded fingerprint SoC.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.1
• /
• pp.14-19
• /
• 2008

Semiconductor testing area challenges many testing issues due to the minimization and ultra high performance of current semiconductors. Among these issues, signal integrity test on interconnections must be solved for highly integrated circuits like SoC. In this paper, we propose an effective pattern application method for signal integrity test on interconnects. Proposed method can be applied by using boundary scan architecture and very efficient test can be preceded with pretty short test time.

• Proceedings of the Korean Society of Computer Information Conference
• /
• 2014.01a
• /
• pp.9-13
• /
• 2014

The performance of large scale software applications has been automatically increasing for last few decades under the influence of Moore's law - the number of transistors on a microprocessor roughly doubled every eighteen months. However, on-chip transistors limitations and heating issues led to the emergence of multicore processors. The energy efficient ARM based System-on-Chip (SoC) processors are being considered for future high performance computing systems. In this paper, we present a case study of two widely used parallel programming models i.e. MPI and MapReduce on distributed memory cluster of ARM SoC development boards. The case study application, Black-Scholes option pricing equation, was parallelized and evaluated in terms of power consumption and throughput. The results show that the Hadoop implementation has low instantaneous power consumption that of MPI, but MPI outperforms Hadoop implementation by a factor of 1.46 in terms of total power consumption to execution time ratio.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.759-761
• /
• 2011

Recently, there is study about interface for user convince. this users interface technology can apply to UI depend on user choice. For that, W3C study various technology which is N-screen service on different device, provide consistent service, and UI adjust service depends on user preference. Therefore, we need UI study based on this model and standard technology. In this paper, study UI technology based on basic model to develop UI for user's convenience. So it can be useful to apply next-generation Web applications and secure web-application measure plans.