• BMB Reports
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• v.53 no.2
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• pp.94-99
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• 2020

Brain cytoplasmic 200 RNA (BC200 RNA) is proposed to act as a local translational modulator by inhibiting translation after being targeted to neuronal dendrites. However, the mechanism by which BC200 RNA inhibits translation is not fully understood. Although a detailed functional analysis of RNA motifs is essential for understanding the BC200 RNA-mediated translation-inhibition mechanism, there is little relevant research on the subject. Here, we performed a systematic domain-dissection analysis of BC200 RNA to identify functional RNA motifs responsible for its translational-inhibition activity. Various RNA variants were assayed for their ability to inhibit translation of luciferase mRNA in vitro. We found that the 111-200-nucleotide region consisting of part of the Alu domain as well as the A/C-rich domain (consisting of both the A-rich and C-rich domains) is most effective for translation inhibition. Surprisingly, we also found that individual A-rich, A/C-rich, and Alu domains can enhance translation but at different levels for each domain, and that these enhancing effects manifest as cap-dependent translation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.233-239
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• 2001

Among the operations in frequency domain for ADSL G.LITE Modem to perform, FFT and FEQ are most computation-intensive part, of which many researches have been focused on the efficient implementation. Previous papers suggested hardwares suitable for ADSL G.DMT system, which is not feasible for simple G.LITE system. The analysis of frequency domain operations and computational efficiency according to the allocation of hardware resources is performed in this paper. The suggested processor has the structure of one real multiplier and two real adders connected in parallel, which can perform the operations efficiently through the pipeline- and/or parallel-type job scheduling. The suggested processor uses less hardware resources than Kiss\`s ALU structure or FFT/IFFT processor suggested by Wang, so the suggested one is more suitable for G.LITE system than previous works.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.1
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• pp.1-9
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• 1993

In recent days high perfermance graphic operation is needed, since computer graphics is widely used for computer-aided design and simulator using high resolution graphic card. In this paper a graphic accelerator is designd with the functions of graphic primitives generation and geometrical transformations. 1-D Systolic Array Processor for Matris Vector operation is designed and used in main ALU of a graphic accelerator, since these graphic algorithms have comonon operation of Matris Vector. Conclusively, in case that the resolution of graphic domain is 800$\times$600, and 33.3nsec operator is used in a graphic accelerator, 29732 lines per second and approximately 6244 circles per second is generated.