• Journal of Animal Science and Technology
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• v.50 no.5
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• pp.633-640
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• 2008

With a double mismatch primer set designed for amplifying the modified DNA sequence fragments, bovine melanocortin-1 receptor(MC1R) gene encoded in Extension locus which plays a critical role in coat color development was analyzed using polymerase chain reaction mediated restriction fragment length polymorphism(PCR-RFLP). Amplified PCR fragments were successfully discriminated with combining the MspI- and AluI-RFLP into three major alleles(ED, E+, and e), directly related to bovine coat color phenotypes. The genotyping results showed that Jeju black cattle contained three MC1R alleles, but yellowish-red colored Hanwoo and bridle colored Korean Brindle cattle did not contained the dominant black allele ED. However, two dominant black-colored cattle breeds, Holstein and Angus, contained the ED allele over 96% in frequency. Hanwoo×Holstein F1 and Hanwoo×Angus F1 crossbred calves showed ED/e MC1R genotypes, and uniformly black coat color. the results suggested that this MC1R genotyping method be useful in allele discrimination for bovine MC1R gene which used for breed classification and characterization, as one of the important genetic markers, using combination of MspI- and AluI-RFLP for modified PCR product amplified with a newly designed double mismatch primer set.

• 한국초전도학회:학술대회논문집
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• v.13
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• pp.15-15
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• 2003

• 한국ITS학회:학술대회논문집
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• v.2007 no.10
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• pp.131-135
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• 2007

• 한국초전도학회:학술대회논문집
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• v.12
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• pp.52-52
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• 2002

• 한국초전도학회:학술대회논문집
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• v.15
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• pp.52-52
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• 2005

• Journal of Advanced Navigation Technology
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• v.18 no.2
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• pp.178-184
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• 2014

CMOS technology based on PCA is very efficient at an implementation of memory or ALU. However, there has been a growing interest in quantum-dot cellular automata (QCA) because of the limitation of CMOS scaling. In this paper, we propose a design of PCA architecture based on QCA. In the proposed PCA design, we utilize D flip-flop and XOR logic gate without wire crossing technique, and design a input and rule control switches. In experiment, we perform the simulation of the proposed PCA architecture by QCADesigner. As the result, we confirm the efficiency the proposed architecture.

• The Transactions of the Korea Information Processing Society
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• v.3 no.1
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• pp.167-180
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• 1996

In the scalar processing oriented machine scalar operations must be performed for the vector processing as many as the number of vector components. So called a vector processing mechanism by the von Neumann operational principle. Accessing vector data hasto beperformed by theevery pointing ofthe instruction or by the address calculation of the ALU, because there is only a program counter(PC) for the sequential counting of the instructions as a memory accessing device. It should be here proposed that an access unit dimensionally to address components has to be designed for the compensation of the organizational hardware defect of the conventional concept. The necessity for the vector structuring has to be implemented in the instruction set and be performed in the mid of the accessing data memory overlapped externally to the data processing unit at the same time.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• Genomics & Informatics
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• v.5 no.2
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• pp.68-76
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• 2007

Due to the increasing interest in SNPs and mutational hot spots for disease traits, it is becoming more important to define and understand the relationship between SNPs and their flanking sequences. To study the effects of flanking sequences on SNPs, statistical approaches are necessary to assess bias in SNP data. In this study we mainly applied Markov chains for SNP sequences, particularly those located in intronic regions, and for analysis of in-del data. All of the pertaining sequences showed a significant tendency to generate particular SNP types. Most sequences flanking SNPs had lower complexities than average sequences, and some of them were associated with microsatellites. Moreover, many Alu repeats were found in the flanking sequences. We observed an elevated frequency of single-base-pair repeat-like sequences, mirror repeats, and palindromes in the SNP flanking sequence data. Alu repeats are hypothesized to be associated with C-to-T transition mutations or A-to-I RNA editing. In particular, the in-del data revealed an association between particular changes such as palindromes or mirror repeats. Results indicate that the mechanism of induction of in-del transitions is probably very different from that which is responsible for other SNPs. From a statistical perspective, frequent DNA lesions in some regions probably have effects on the occurrence of SNPs.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.31-38
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• 2003

A 16-bit adiabatic low-power Microprocessor is designed. The processor consists of control block, multi-port register file, program counter, and ALU. An efficient four-phase clock generator is also designed to provide power clocks for adiabatic processor. Adiabatic circuits based on efficient charge recovery logic(ECRL), are designed 0.35,${\mu}{\textrm}{m}$ CMOS technology. Conventional CMOS processor is also designed to compare the energy consumption of microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is reduced by a factor of 2.9∼3.1 compared to that of conventional CMOS microprocessor.