• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.194-198
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• 2003

A 16-bit adiabatic low-power Micro-processor core is designed. The processor consists of control block, multi-port register file and ALU. A simplified four-phase clock generator is designed to provide supply clocks for adiabatic processor. All the clock line charge on the capacitive interconnections is recovered to recycle the energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and $0.35\mu\textrm$ CMOS technology is used. Simulation results show that the power consumption of the adiabatic Microprocessor core is reduced by a factor of 2.9~3.1 compared to that of conventional CMOS Microprocessor

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.1-10
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• 1998

The first thing in designing application-specific instruction set processor is having instruction set closely matching hardware characteristics. This instruction set design problem can be more complicated when cobined with implementation method selection problem of each instruction. Our processor model supports two kinds of instructions-primitive or special instructions. Primitive instructions are implemented using common multifunctional hardware such as ALU. Special instructions require a set of dedicated hardware, which actually functions as a coprocessor to the main processor. In this case, special instructions and primitive instructions can be executed independently. In this paper, we present novel algorithm for genrating special instructions for given application. Parallelism between special instructions and primitive instructions is also considered during the performance estimation stage of generated special instructions.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.9-12
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• 2001

본 논문에서는 유럽 통신 표준화기구인 ETSI 의 SMGll에서 채택된 GSM Full Rate(FR) 보코더 알고리wma[1]을 Teak DSP Core를 이용하여 실시간 구현하였다. GSM FR 보코더는 유럽에서 사용하는 통신 시스템인 GSM 의 full-rate Traffic Channel(TCH)의 표준 코덱[2]으로서 GSM HR, GSM EFR GSM AMR과 더불어 모뎀칩 내에 장착되는 필수적인 음성 서비스이다. 구현된 GSM FR는 13.05kbps의 비트율을 가지고 있으며, 인코더와 디코더 기능 외에 voice activity detection(VAD)[3]블록과 DTX[4]블록 등의 부가 기능도 구현되어 있다. 구현에 사용된 Teak[5]는 DSP Group 의 16bit고정 소수점 DSP core로서 최대 140MIPS 의 성능을 낼 수 있고 400bits ALU 와 두개의 MAC 이 장착되어 있어 음성 및 채널 부호화기의 실시간 처리에 최적화 되어있다. 구현된 GSM FR 은 인코더와 디코더 부분이 각각 약 235 MIPS 및 1.19MIPS 의 복잡도를 나타내며, 사용된 메모리는 프로그램 ROM 3.9K words, 데이터 ROM(table) 396 words 및 RAM 932words이다.

• Journal of the Korean Ceramic Society
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• v.35 no.12
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• pp.1308-1315
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• 1998

Effects of particle size of alumina on densification behavior during liquid-phase sintering of alumina-talc system were investigated with emphasis on particle rearrangement process. In the case of using coarse alu-mina powder densiication of specimens was rapidly accelerated after formation of liquid phase due to easy particle rearrangement process with addition of talc and increase of sintering temperature. On the contrary when fine alumina powder was used premature densification of alumina matrix region formed before for-mation of liquid phase rigid skeleton structure and then it seemed to inhibit rearrangement process during crease of sintering temperature. As results the densification of specimens using coarse alumina powder was higher than that of the case of using fine one.

• Journal of the Korean Ceramic Society
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• v.35 no.12
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• pp.1266-1273
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• 1998

Al2O3/(5~20vol%)LaAl11O18 composites in which the second phase was dispersed with a elongated grain shape were fabricated using Al2O3 and La2O3 composition by hot-pressing. In order investigate the in-fluence of LaAl11O18 on the toughening of LaAl11O18 on the toughening of Al2O3 matrix composites AE(acoustic emission) analysis was con-ducted together with an evaluation of fracture toughness using of SEPB technique. The degree of AE events occurred in composites were more than those in monolithic alumina. The occurrences of AE event increased with increasing the amount of LaAl11O18 phase in the Al2O3/LaAl11O18 composite is two times higher compared to monolithic alu-mina. The main toughening mechanism was attributed to the bridging of LaAl11O18 grains at tip of pro-pagating crack.

• Animal cells and systems
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• v.7 no.3
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• pp.249-253
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• 2003

Abnormalities in fibrinolysis system is associated with risk of hypertension. In this report, the Alu repeat insertion/deletion (I/D) polymorphism of tissue plasminogen activator (t-PA) and the Hind III RFLP of plasminogen activator inhibitor-1 (PAI-1) genes were investigated in 115 normotensives and 83 patients with hypertension, and their association with anthropometrical data and plasma biochemical parameters were analyzed. There were no significant differences in the gene frequencies of the two candidate genes between normotensives and hypertensives, respectively. Our results indicate lack of associations between the two polymorph isms in t-PA and PAI-1 genes and risk of hypertension in the population under study. However, the Hind III RFLP of PAI-1 gene was significantly associated with plasma glucose level, suggesting its role in glucose metabolism. It needs to be tested whether this RFLP of PAI-1 gene is associated with insulin resistance syndrome or non-insulin dependent diabetes mellitus (NIDDM) in the Korean population.

• Journal of Microbiology and Biotechnology
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• v.16 no.9
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• pp.1472-1476
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• 2006

Previous study demonstrated that the restriction barrier of Streptomyces griseus is almost completely bypassed by the Streptomyces-E. coli shuttle vectors passed through the E. coli GM161 strain and methylated with AluI and HpaII methyltransferases. The same DNA methylation of the genomic DNA fragments cloned the nonreplicative vectors generated integrative transformation and gene disruption of their chromosomal counterparts at high efficiencies in S. griseus. This result indicated that the efficiency of gene disruption depends on the efficient transfer of the incoming DNA into bacterial hosts.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1015-1024
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• 1990

This paper proposes a program counter unit(PCU) on the pipelined architecture of RISC (Reduced Instruction Set Computer) type high performance processors, PCU is used for supplying instruction addresses to memory units(Instruction Cache) efficiently. A RISC processor's PCU has to compute the instruction address within required intervals continnously. So, using the method of self-generated incrementor, is more efficient than the conventional one's using ALU or private adder. The proposed PCU is designed to have the fast +4(Byte Address) operation incrementor that has no carry propagation delay. Design specifications are taken by analyzing the whole data path operation of target processor's default and exceptional mode instructions. CMOS and wired logic circuit technologic are used in PCU for the fast operation which has small layout area and power dissipation. The schematic capture and logic, timing simulation of proposed PCU are performed on Apollo W/S using Mentor Graphics CAD tooks.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• Journal of the Korean Ceramic Society
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• v.35 no.6
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• pp.551-558
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• 1998

Detection of microcrack in {{{{ {Al }_{2 } {O }_{3 } }} ceramics were studided by AE(acoustic emission) technique with 4-point bending test in order to evaluate the fracture process and formation of microcrack. Fully-dense alu-mina ceramics having a different grain size were fabricated by varing the hot-pressing temperature. The grain size of alumina increased with increasing the hot-pressing temperature whereas the bending strength decreasd. The microcracks were observed by SEM and TEM. The generation of AE event increased with increasing the applied load and many AE event was generated at maximum applied load. Alumina with smaller grain size shows the generation of many AE event resulting in an increase of microcrack formation. An intergranular fracture is predominantly observed in fine-grained alumina whereas intragranular fracture occurs predominantly in coarse-grained alumina,. Analysis of micorstructure and AE prove that primary mi-crocracks occur within grain-boundaries of alumina. The larger microcracking were formed by the growth and/or coalesence of primary microcracks. Then the materials become to fracuture by main crack gen-eration at the maximum applied load.