• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.277-280
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• 2000

In this paper, we designed a turbo decoder using VHDL. To maximize effective free distance of the turbo code, we implemented pseudo random interleaver. A MAP(Maximum a posteriori) decoder is used as a primimary decoder. We avoided multiplication by using lookup tables(ROM). We expect that this small-sized turbo decoder is suitable for mobile communication. We simulated turbo decoder with Altera MAX+PLUS II.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.293-296
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• 2000

In this paper, we designed a 192-tap echo canceller for a modem using VHDL. To evaluate errors, we used adaptive algorithm. We adopted pipeline technique and realized delay-taps with RAMs. We simulated this design using Altera MAX+PLUS II.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.301-304
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• 2000

In this paper, we designed a 256-point FFT processor using VHDL. We adopted Radix-2$^2$SDC(Single-path Delay Commutator) architectures to reduce the number of complex multipliers. We confirmed the operation of the design through simulation using Altera MAX+PLUS II.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.855-858
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• 1999

In this paper, we present a FPCA implementation of IDEA algorithm. Target technology is Altera FLEX 10K FPCA. The correctness of the implementation is verified by the timing simulation with max+plus II.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.727-730
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• 2002

최근 키를 가지고 다니는 불편함과 보안성을 고려한 전자 키들이 많이 생산되고 있다. 키의 불편함과 보안성을 보완하는 방법에는 비밀번호 입력, 지문인식, 홍체인식 등의 방법이 이용되고 있는데, 본 논문에서는 비밀번호를 입력하는 방법으로 설계하였다. Altera사의 Software인 MAXPLUS II를 이용하여 설계하였고, Hardware Language인 VHDL을 이용하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.107-112
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• 2012

In this contribution, we designed a general purpose input/output (GPIO) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. General purpose I/O should be used as multi-functional and versatile interrupt sources. We considered the edge-sensitive mode as well as the level-sensitive mode for acquiring the interrupt sources. Also, we provided an option to select the operation polarity for flexible application to the embedded systems. The designed GPIO module was automatically synthesized, placed, and routed. The proposed GPIO was implemented through the Altera FPGA and well operated at 25MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.3 s.309
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• pp.50-58
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• 2006

This paper describes the implementation of an efficient Rate-Distortion Optimization algerian to speed up rate control in JPEG2000. While the conventional algorithm determines the rate constant by averaging maximum R-D slope and minimum R-D slope for entire image, the proposed algorithm determines it by using R-D slopes of coding passes located near truncation point. Moreover, the rate allocation in proposed algorithm is conducted about only coding passes excluded from the previous rate allocation. As a result, it can reduce the number of operations required for rate-distortion optimization. The proposed algorithm was implemented in C programing language and was executed on the Altera Excalibur(EPXA4) development board.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.11
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• pp.28-36
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• 1998

In the CDMA mobile communication system with asynchronous mode among base stations, the initial PN code acquisition method using a matched filter can be considered for the rapid PN code synchronization acquisition in the handoff region. In the model of the noncoherent QPSK/DS-SS under the Rayleigh fading channel, the mean acquisttion time of the matched filter is analyzed to have a shortened time in proportion to the length of matched filter to be compared with the serial correlation method. In this paper to improve the HW complexity of the conventional matched device which enables the repeated correlation process, is designed and its function is verified through the FPGAsimulation using Altera MaxPlus Ⅱ.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.5
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• pp.2322-2326
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• 2011

General cryptosystem uses differently the data and key value for the increment of security level, processes the repetition of limited number and increases the periodic feature of LFSR similar infinite series. So, it cause the efficiency of the cryptosystem. In this thesis, proposed algorithm is composed of reformat, permutation, data cipher block and key scheduler which is applied the new function by mixed symmetric cryptography and asymmetric cryptography. We design the cryptosystem of smart card using the common Synopsys and simulate by ALTERA MAX+PLUS II at 40MHz. Consequently, we confirm the 52% increment of processing rate and the security level of 16 rounds.

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.3
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• pp.150-156
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• 2007

In this paper, we studied security systems for information security of several systems that use in network environment along with information society. Therefore, we designed symmetry style base mixing style cryptographic system that apply block and stream way to solve problems of complexity and lower processing speed etc. Symmetry style base mixing style cryptographic system including authentication operation holds performance that the processing speed and the calculation amount are more superior than asymmetry style. Result that design system by Synopsys 1999.10 and ALTERA MaxPlus 10.1 and do simulation, mixing style password system that we propose is that information security offers very efficient assistance and performance in necessary field in network environment.