• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.11-11
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• 2010

Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.126-126
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• 2000

다이아몬드상 카본(DLC) 필름은 경도가 높고, 마찰계수가 낮다는 장점을 가지고 있기 때문에 내마모성 코팅이나 윤활성코팅에 응용을 위한 연구가 활발히 진행중이다. 하지만 마찰계수가 주변환경에 매우 큰 영향을 받는다는 단점이 있다. 이러한 단점은 DLC필름의 응용에 대한 저해 요인이 되며, 이 점을 보완하기 위해서 DLC 필름에 Si을 첨가하는 연구들이 진행되고 있다. 본 실험에서는 r.f-PACVD 법을 이용하여 Si이 첨가된 DLC 필름의 주위 환경 변화에 따른 마찰특성의 변화를 연구하였다. 사용한 반응 가스는 벤젠(C6H)과 희석된 Silane(SiH4 : H2 = 10 : 90)이며, 희석된 Silane과 벤젠의 첨가비율을 조절하여 필름내 Si의 함량을 조절하였고, 증착시 바이아스의 전압은 -400V로 하였다. 마찰테스트는 Ball-on-Disk type의 조건에서 대기, 건조공기, 진공의 세가지 분위기에서 마찰테스트를 실행하였다. 실험결과 마찰계수는 건조공기, 대기, 진공의 순으로 증가하였고, 필름내에 포함되어 있는 Si의 양이 증가할수록 마찰계수는 낮고 안정한 값을 나타내었다. Tribochemiacal 분석과, ball과 track의 전자현미경 사진 분석 결과, 진공에 비해서 건조공기와 대기중에서 마찰계수가 낮은 것은 DLC 필름내에 마모 track 중심부에 Si-C-O 계의 화합물이 형성되어, 이 화합물이 마찰계면에 존재하여 마찰계수를 낮추었음을 확인하였다. 그리고 대기중에서 실험한 경우, 습기의 존재로 인해 마모입자가 볼의 표면에서 엉김으로써 건조공기의 상태에서 보다 높은 마찰저항을 갖게 됨으로 인하여 마찰계수가 높아짐을 알 수 있었다.a)는 as-deposit 상태이며, 그림 1(b)는 45$0^{\circ}C$, 60min 열처리한 plan-view TEM 사진이다.dical의 영향을 조사하였으며 oxygen radical의 rf power에 따른 변화는 OES(Optical emission spectroscopy)를 사용하였다. 너무 적은 oxygen ion beam flux나 oxygen radical은 film의 전도도 및 투과도를 저하시켰고 반면 너무 과도한 flux의 증가 시는 전도도는 감소하였고 투과도는 증가하는 경향을 보였다. 기판에 도달하는 oxygen ion flux는 faraday cup을 이용하여 측정하였으며 증착된 ITO film은 XPS, UV-spectrometer, 4-point probe를 이용하여 분석하였다. 때문으로 생각되어진다. 또한, 성장 온도가 낮아짐에 따라 AlGaN의 성장을 저해하기 때문으로 판단된다. 성장 온도 변화에 따라 성장된 V의 구조적 특성 및 표면 거칠기 변화를 관찰하여 AlGaN의 성장 거동을 논의하겠다.034, 0.005 정도로 다시 감소하였다. 박막의 유전율은 약 35 정도의 값을 나타내었으며 X-선 회절 data로부터 분석한 박막의 변형은 증온도에 따라 7.2%에서 0.04%로 감소하였고 이 이경향은 유전손실은 감소경향과 일치하였다.는 현저하게 향상되었다. 그 원인은 SB power의 인가에 의해 활성화된 precursor 분자들이 큰 에너지를 가지고 기판에 유입되어 치밀한 박막이 형성되었기 때문으로 사료된다.을수 있었다.보았다.다.다양한 기능을 가진 신소재 제조에 있다. 또한 경제적인 측면에서도 고부가 가치의 제품

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.53-60
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• 2014

Different kinds of post-deposition annealing (PDA) by a rapid thermal process (RTP) are used to enhance the field-effect passivation of $Al_2O_3$ film in crystal Si solar cells. To characterize the effects of PDA on $Al_2O_3$ and the interface, metal-insulator semiconductor (MIS) devices were fabricated. The effects of PDA were characterized as functions of RTP temperature from $400{\sim}700^{\circ}C$ and RTP time from 30~120 s. A high temperature PDA can retard the passivation of thin $Al_2O_3$ film in c-Si solar cells. PDA by RTP at $400^{\circ}C$ results in better passivation than a PDA at $400^{\circ}C$ in forming gas ($H_2$ 4% in $N_2$) for 30 minutes. A high thermal budget causes blistering on $Al_2O_3$ film, which degrades its thermal stability and effective lifetime. It is related to the film structure, deposition temperature, thickness of the film, and annealing temperature. RTP shows the possibility of being applied to the PDA of $Al_2O_3$ film. Optimal PDA conditions should be studied for specific $Al_2O_3$ films, considering blistering.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.327.1-327.1
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• 2014

Nitrides-on-silicon structures are considered to be an excellent candidate for unique design architectures and creating devices for high-power applications. Therefore, a lot of effort has been concentrating on growing high-quality III-nitrides on Si substrates, mostly Si(111) and Si(001) substrates. However, there are several fundamental problems in the growth of nitride compound semiconductors on silicon. First, the large difference in lattice constants and thermal expansion coefficients will lead to misfit dislocation and stress in the epitaxial films. Second, the growth of polar compounds on a non-polar substrate can lead to antiphase domains or other defective structures. Even though the lattice mismatches are reached to 16.9 % to GaN and 19 % to AlN and a number of dislocations are originated, Si(111) has been selected as the substrate for the epitaxial growth of nitrides because it is always favored due to its three-fold symmetry at the surface, which gives a good rotational matching for the six-fold symmetry of the wurtzite structure of nitrides. Also, Si(001) has been used for the growth of nitrides due to a possible integration of nitride devices with silicon technology despite a four-fold symmetry and a surface reconstruction. Moreover, Si(110), one of surface orientations used in the silicon technology, begins to attract attention as a substrate for the epitaxial growth of nitrides due to an interesting interface structure. In this system, the close lattice match along the [-1100]AlN/[001]Si direction promotes the faster growth along a particular crystal orientation. However, there are insufficient until now on the studies for the growth of nitride compound semiconductors on Si(110) substrate from a microstructural point of view. In this work, the microstructural properties of nitride thin layers grown on Si(110) have been characterized using various TEM techniques. The main purpose of this study was to understand the atomic structure and the strain behavior of III-nitrides grown on Si(110) substrate by molecular beam epitaxy (MBE). Insight gained at the microscopic level regarding how thin layer grows at the interface is essential for the growth of high quality thin films for various applications.

• Korean Journal of Materials Research
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• v.31 no.12
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• pp.727-731
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• 2021

In this study, we have investigated a selective emitter using a UV laser on BBr₃ diffusion doping layer. The selective emitter has two regions of high and low doping concentration alternatively and this structure can remove the disadvantages of homogeneous emitter doping. The selective emitters were fabricated by using UV laser of 355 nm on the homogeneous emitters which were formed on n-type Si by BBr₃ diffusion in the furnace and the heavy boron doping regions were formed on the laser regions. In the optimized laser doping process, we are able to achieve a highly concentrated emitter with a surface resistance of up to 43 Ω/□ from 105 ± 6 Ω/□ borosilicate glass (BSG) layer on Si. In order to compare the characteristics and confirm the passivation effect, the annealing is performed after Al₂O₃ deposition using an ALD. After the annealing, the selective emitter shows a better effect than the high concentration doped emitter and a level equivalent to that of the low concentration doped emitter.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.14 no.6
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• pp.244-252
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• 2004

A stoichiometric mixture of evaporating materials for $CuInSe_2$ single crystal thin films was prepared from horizontal electric furnace. To obtain the single crystal thin films, $_CuInSe2$ mixed crystal was deposited on thoroughly etched semi-insulating GaAs(100) substrate by the hot wall epitaxy (HWE) system. The source and substrate temperatures were $620^{\circ}C$ and $410^{\circ}C$, respectively. The crystalline structure of the single crystal thin films was investigated by the photoluminescence and double crystal X-ray diffraction (DCXD). The carrier density and mobility of $CuInSe_2$ single crystal thin films measured with Hall effect by van der Pauw method are $9.62\times10^{16}/\textrm{cm}^3$, 296 $\textrm{cm}^2$/Vㆍs at 293 K, respectively. The temperature dependence of the energy band gap of the $CuInSe_2$ obtained from the absorption spectra was well described by the Varshni's relation, $E_g$(T) = 1.1851 eV -($8.99\times10^{-4} eV/K)T^2$(T + 153 K). The crystal field and the spin-orbit splitting energies for the valence band of the CuInSe$_2$ have been estimated to be 0.0087 eV and 0.2329 eV at 10 K, respectively, by means of the photocurrent spectra and the Hopfield quasicubic model. These results indicate that the splitting of the Δso definitely exists in the $\Gamma$6 states of the valence band of the $CuInSe_2$. The three photocurrent peaks observed at 10 K are ascribed to the $A_1-, B_1$-와 $C_1$-exciton peaks for n = 1.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.

• Tribology and Lubricants
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• v.35 no.5
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• pp.274-285
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• 2019

Chemical mechanical polishing (CMP), which is a material removal process involving chemical surface reactions and mechanical abrasive action, is an essential manufacturing process for obtaining high-quality semiconductor surfaces with ultrahigh precision features. Recent rapid growth in the industries of digital devices and semiconductors has accelerated the demands for processing of various substrate and film materials. In addition, to solve many issues and challenges related to high integration such as micro-defects, non-uniformity, and post-process cleaning, it has become increasingly necessary to approach and understand the processing mechanisms for various substrate materials and abrasive particle behaviors from a tribological point of view. Based on these backgrounds, we review recent CMP R&D trends in this study. We examine experimental and analytical studies with a focus on substrate materials and abrasive particles. For the reduction of micro-scratch generation, understanding the correlation between friction and the generation mechanism by abrasive particle behaviors is critical. Furthermore, the contact stiffness at the wafer-particle (slurry)-pad interface should be carefully considered. Regarding substrate materials, recent research trends and technologies have been introduced that focus on sapphire (${\alpha}$-alumina, $Al_2O_3$), silicon carbide (SiC), and gallium nitride (GaN), which are used for organic light emitting devices. High-speed processing technology that does not generate surface defects should be developed for low-cost production of various substrates. For this purpose, effective methods for reducing and removing surface residues and deformed layers should be explored through tribological approaches. Finally, we present future challenges and issues related to the CMP process from a tribological perspective.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.37-43
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• 2008

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program/erase (P/E) speed, reliability of memory device on interface trap between Si substrate and tunneling oxide and bulk trap in nitride layer were investigated using charge pumping method which has advantage of simple and versatile technique. We analyzed different SANOS memory devices that were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SANOS cell transistors with larger capture cross section and interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. The data retention was deteriorated as increasing P/E cycling number but not coincides with interface trap increasing tendency. This result once again confirmed that interface trap independence on data retention. And the result on different program method shows that HCI program method more degraded by locally trapping. So, we know as a result of experiment that analysis the SANOS Flash memory characteristic using charge pumping method reflect the device performance related to interface and bulk trap.