• 한국재료학회지
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• 제16권4호
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• pp.253-256
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• 2006

The blue emitting OLEDs using GDI host-dopant phosphors have been fabricated and characterized. In the device fabrication, 2-TNATA [4,4',4'-tris(2-naphthylphenyl-phenylamino)- triphenylamine] as a hole injection material and NPB [N,N'-bis(1-naphthyl)-N,N'-diphenyl-1,1'-biphenyl-4,4'-diamine] as a hole transport material were deposited on the ITO(indium thin oxide)/glass substrate by vacuum evaporation. And then, blue color emission layer was deposited using GDI602 as a host material and GDI691 as a dopant. Finally, small molecule OLEDs with structure of ITO/2-TNATA/NPB/GDI602:GDI691/Alq3/LiF/Al were obtained by in-situ deposition of Alq3, LiF and Al as the electron transport material, electron injection material and cathode, respectively. Blue OLEDs fabricated in our experiments showed the color coordinate of CIE(0.14, 0.16) and the maximum power efficiency of 1.1 lm/W at 11 V with the peak emission wavelength of 464 nm.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• 한국정보통신학회논문지
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• 제6권2호
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• pp.315-322
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• 2002

반도체 제조공정과 미세가공 기술을 이용하여 30$0^{\circ}C$의 동작온도에서 약 60㎽의 전력소모를 갖는 산화물 반도체 박막 가스센서 어레이를 제조하였다. 멤브레인의 우수한 열적 절연은 0.1$\mu\textrm{m}$ 두께의 Si$_3$N$_4$와 1$\mu\textrm{m}$ 두께의 PSG의 이중 층에 의한 것으로, 각각 LPCVD(저압화학 기상증착)와 APCVD(대기압 화학 기상증착)에 의해 제조되었다. 센서 어레이의 4가지 산화물 반도체 박막 감지물질로는 1wt.%Pd가 도핑된 SnO$_2$, 6wt.% $Al_2$O$_3$가 도핑된 ZnO, WO$_3$, ZnO를 이용하였으며, 제조된 초소형 산화물 반도체 박막 가스센서 어레이는 여러 가지 가스의 노출시 유용한 저항 변화를 나타내었고 감도는 감지 물질에 강하게 의존함을 알 수 있었다. 센서 소자의 공정 수율을 증진시키기 위하여 히터 부위를 함몰하는 공정 방법을 취하였으며, 그 결과 월등한 수율 개선을 도모할 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.171-171
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• 2012

We have studied the effects of plasma treatments on CdS buffer layers in CIGS thin film solar cells. The CdS layers were deposited on CIGS films by chemical bath deposition (CBD) method. The RF plasma treatments of the CdS thin films were performed with Ar, $O_2 and $N_2 gases, respectively. After plasma treatments, the solar cells with Al:ZnO/i-ZnO/CdS/CIGS structures were fabricated. The surface properties of the CdS/CIGS thin films after plasma treatments were investigated with SEM, EDX and AFM measurements. The electrical properties of manufactured solar cell were discussed with the results of current-voltage measurements. The plasma treatments have a strong influence on the open circuit voltage (VOC) and the fill factor of the solar cells. Finally, a correlation between the surface properties of CdS layer and the efficiencies of the CIGS thin film solar cells is discussed.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.156-156
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• 2000

Recently, the surface electronic states have attracted much attention since their standing wave patterns created around steps, defects, and adsorbates on noble metal surfaces such as Au(111), Ag(110), and Cu(111) were observed by scanning tunneling microscopy (STM). As a typical example, a striking circular pattern of "Quantum corral" observed by Crommie, Lutz, and Eigler, covers a number of text books of quantum mechanics, demonstrating a wavy nature of electrons. After the discoveries, similar standing waves patterns have been observed on other metal and demiconductor surfaces and even on a side polane of nano-tubes. With an expectation that the surface states could be utilized as one of ideal cases for studying two dimensionakl (sD) electronic system, various properties, such as mean free path / life time of the electronic states, have been characterized based on an analysis of standing wave patterns, . for the 2D electron system, electron density is one of the most importnat parameters which determines the properties on it. One advantage of conventional 2D electron system, such as the ones realized at AlGaAs/GaAs and SiO2/Si interfaces, is their controllability of the electrondensity. It can be changed and controlled by a factor of orders through an application of voltage on the gate electrode. On the other hand, changing the leectron density of the surface-state 2D electron system is not simple. On ewqy to change the electron density of the surface-state 2D electron system is not simple. One way to change the electron density is to deposit other elements on the system. it has been known that Pd(111) surface has unoccupied surface states whose energy level is just above Fermi level. Recently, we found that by depositing Pd on Cu(111) surface, occupied surface states of Cu(111) is lifted up, crossing at Fermi level around 2ML, and approaches to the intrinsic Pd surface states with a increase in thickness. Electron density occupied in the states is thus gradually reduced by Pd deposition. Park et al. also observed a change in Fermi wave number of the surface states of Cu(111) by deposition of Xe layer on it, which suggests another possible way of changing electron density. In this talk, after a brief review of recent progress in a study of standing weaves by STM, I will discuss about how the electron density can be changed and controlled and feasibility of using the surface states for a study of 2D electron system. One of the most important advantage of the surface-state 2D electron system is that one can directly and easily access to the system with a high spatial resolution by STM/AFM.y STM/AFM.

• 대한금속재료학회지
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• 제47권11호
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• pp.728-733
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• 2009

Cu based amorphous ($Cu_{54}Zr_{22}Ti_{18}Ni_{6}$) powders were deposited onto Al 6061 substrates by cold spray process with different powder preheating temperatures (below glass transition temperature: $350^{\circ}C$, near glass transition temperature: $430^{\circ}C$ and near crystallization temperature: $500^{\circ}C$). The microstructure and macroscopic properties (hardness, wear and corrosion) of Cu based amorphous coating layers were also investigated. X-ray diffraction results showed that cold sprayed Cu based amorphous coating layers of $300{\sim}350{\mu}m$ thickness could be well manufactured regardless of powder preheating temperature. Porosity measurements revealed that the coating layers of $430^{\circ}C$ and $500^{\circ}C$ preheating temperature conditions had lower porosity contents (0.88%, 0.93%) than that of the $350^{\circ}C$ preheating condition (4.87%). Hardness was measured as 374.8 Hv ($350^{\circ}C$), 436.3 Hv ($430^{\circ}C$) and 455.4 Hv ($500^{\circ}C$) for the Cu based amorphous coating layers, respectively. The results of the suga test for the wear resistance property also corresponded well to the hardness results. The critical anodic current density ($i_{c}$) according to powder preheating temperature conditions of $430^{\circ}C$, $500^{\circ}C$ was lower than that of the sample preheated at $350^{\circ}C$, respectively. The higher hardness, wear and corrosion resistances of the preheating conditions of near $T_{g}$ and $T_{x}$, compared to the properties of below $T_{g}$, could be well explained by the lower porosity of coating layer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권4호
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• pp.202-208
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• 2001

In Recent results suggested that doping $Ta_2O_5$ with a small amount of $TiO_2$ using standard ceramic processing techniques can increase the dielectric constant of $Ta_2O_5$ significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped $Ta_2O_5$ films are deposited using $TaC_{12}H_{30}O_5N$, $C_8H_{24}N_4Ti$, and $O_2$ on both Si and $NH_3$-nitrided Si substrates. An $NH_3$-based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in $H_2/O_2$ ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the $TaTi_xO_y$ dielectric. XPS analyses confirm the formation of a ($Ta_2O_5)_{1-x}(TiO_2)_x$ composite oxide. A high quality $TaTi_xO_y$ gate stack with EOT (Equivalent Oxide Thickness) of $7{\AA}$ and leakage current $Jg=O.5A/textrm{cm}^2$ @ Vg=-1.0V has been achieved. We have also succeeded in forming a $TaTi_x/O_y$ composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD $Ta_2O_5, suggesting that the dielectric constant of $Ta_2O_5$ is not affected by the addition of $TiO_2$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1297-1298
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• 2006

Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have been attracted recently attention due to their highdevice performance expected from theoretical simulations among nanowire-based FETs with other gate geometries. OSG FETs with the channels of ZnO nanowires were successfully fabricated in this study with photolithographic processes. In the OSG FETs fabricated on oxidized Si substrates, the channels of ZnO nanowires with diameters of about 60 nm are coated surroundingly by $Al_{2}O_{3}$ as gate dielectrics with atomic layer deposition. About 80 % of the surfaces of the nanowires coated with $Al_{2}O_{3}$ is covered with gate metal to form OSG FETs. A representative OSG FET fabricated in this study exhibits a mobility of 98.9 $cm^{2}/Vs$, a peak transconductance of 0.4 ${\mu}S$, and an Ion/Ioff ratio of $10^6$ the value of the Ion/Ioff ratio obtained from this OSG FET is the highest among nanowire-based FETs, to our knowledge. Its mobility, peak transconductance, and Ion/Ioff ratio arc remarkably enhanced by 11.5, 32, and $10^6$ times, respectively, compared with a back-gate FET with the same ZnO nanowire channel as utilized in the OSG FET.

• 한국결정성장학회지
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• 제9권2호
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• pp.212-216
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• 1999

SiC(3C) 광다이오드는 p-형 Si 위에 tetramethylsilane (TMS)를 열분해아여 화학기상증착법으로 성장된 SiC(3C) 에피층을 성장하여 제작되었다. SiC(3C)의 전기적 특성은 홀 측정(Hall measurement) 및 전류-전압(I-V) 특성으로 조사되었다. SiC(3C) 에피층의 전도형은 n-형이었다. 저항성 접촉은 마스크 (shadow-mask)를 통해서 Al을 열증착하여 형성하였다. SiC(3C)광다이오드의 광학적 이득(photovoltaic detection)를 해석하기 위하여 SiC(3C) 에피층의 Spectral response (SR)를 전기적 변수(electrical parameter) 및 광다이오드의 기하학적 구조(geometric structure)를 고려하여 계산하였다. 적절히 선정된 변수들로부터 계산된 SR의 최대값은 550 nm에서 약 0.75이었고, 파장영역 400~600 nm 사이에서 청색 및 근자외선 광검지기로서 매우 유용하다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.289-289
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• 2013

While there are plenty of studies on synthesizing semiconducting germanium nanowires (Ge NWs) by vapor-liquid-solid (VLS) process, it is difficult to inject dopants into them with uniform dopants distribution due to vapor-solid (VS) deposition. In particular, as precursors and dopants such as germane ($GeH_4$), phosphine ($PH_3$) or diborane ($B_2H_6$) incorporate through sidewall of nanowire, it is hard to obtain the structural and electrical uniformity of Ge NWs. Moreover, the drastic tapered structure of Ge NWs is observed when it is synthesized at high temperature over $400^{\circ}C$ because of excessive VS deposition. In 2006, Emanuel Tutuc et al. demonstrated Ge NW pn junction using p-type shell as depleted layer. However, it could not be prevented from undesirable VS deposition and it still kept the tapered structures of Ge NWs as a result. Herein, we adopt $C_2H_2$ gas in order to passivate Ge NWs with carbon sheath, which makes the entire Ge NWs uniform at even higher temperature over $450^{\circ}C$. We can also synthesize non-tapered and uniformly doped Ge NWs, restricting incorporation of excess germanium on the surface. The Ge NWs with carbon sheath are grown via VLS process on a $Si/SiO_2$ substrate coated 2 nm Au film. Thin Au film is thermally evaporated on a $Si/SiO_2$ substrate. The NW is grown flowing $GeH_4$, HCl, $C_2H_2$ and PH3 for n-type, $B_2H_6$ for p-type at a total pressure of 15 Torr and temperatures of $480{\sim}500^{\circ}C$. Scanning electron microscopy (SEM) reveals clear surface of the Ge NWs synthesized at $500^{\circ}C$. Raman spectroscopy peaked at about ~300 $cm^{-1}$ indicates it is comprised of single crystalline germanium in the core of Ge NWs and it is proved to be covered by thin amorphous carbon by two peaks of 1330 $cm^{-1}$ (D-band) and 1590 $cm^{-1}$ (G-band). Furthermore, the electrical performances of Ge NWs doped with boron and phosphorus are measured by field effect transistor (FET) and they shows typical curves of p-type and n-type FET. It is expected to have general potentials for development of logic devices and solar cells using p-type and n-type Ge NWs with carbon sheath.