• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.232-232
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• 2010

Simulation Program (AFORS-HET 2.4.1) was used, include the basic structure of crystalline silicon thin film as above, under the intrinsic a-Si:H films bonded symmetrical structure (Symmetrical structure) were used. The structure of ITO, a-Si p-type, intrinsic a-Si, c-Si, intrinsic a-Si, a-Si n-type, metal (Al) layer has one of the seven. When thickness for each layer was given the change, the changes of a-Si p-type layer and the intrinsic a-Si layer on top had an impact on efficiency. Efficiency ratio of p-type a-Si:H layer thickness was sensitive to, especially a-Si: H layer thickness is increased in a rapid decrease in Jsc and FF, and efficiency was also decreased.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.3-6
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• 2002

In this paper, Thin film bulk acoustic resonate.(TFBAR) fillers tuned by gold plated on-wafer inductors are presented. The air-gap type TEBAR is used with aluminum nitride(AIN) as piezoelectric material and platinum as top and bottom electrodes. Inductor equivalent model and modified Butterworth-Van Dyke(MBVD) model are employed for the frequency tuning of fabricated TFBAR bandpass filters. Fabricated inductor has inductance of 3 nH and Q factor of about 8 at 2 ㎓. It is clearly revealed that inductor tuning can enhance the bandwidth of ladder filters and improve out-of-band rejection characteristic around 10㏈.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.11a
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• pp.49-54
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• 1992

Devices of ITO/CdS/CdTe/Te/Al were prepared by Electron-Beam deposition under a vacuum of $7{\times}10^{-6}$[torr]. Optical, Electrical, Structural and Photovoltaic properties of thin film CdS/CdTe at substrate. temperature 300~500[$^{\circ}C$] were also investigated, The structure of CdTe films deposited was of the zincblende type a preferential orientation of the (111) plane parallel to the substrate, the CdTe dark resistivity was about $10^6[{\Omega}cm]$. The conversion, efficiency of the cell increased with increasing substrate temperature. The best-fabricated Cell was a conversion efficiency of 9.1[%].

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.45-46
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• 2005

The piezoelectric ZnO thin films were deposited onto Al/Si substrate in order to figure out the crystalline and the residual stress of deposited films. As the $Ar/O_2$ gas ratio is increased, c-axis orientation of deposited films is significantly enhanced and also the residual stresses of ZnO films are all compressive. They are decreased from -1.2 GPa to -950 MPa as the $Ar/O_2$ gas ratio is increased. A diaphragm-based piezoelectric microspeaker fabricated on ONO films shows about 14 mPa output pressure at 1 kHz with $8V_{peak-to-peak}$.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.05a
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• pp.149-149
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• 2009

실제 산업에서 가장 많이 사용하고 있는 in-line type system에서 Al-doped ZnO (AZO) 막을 bipolar pulsed DC sputtering을 이용해 증착하였다. 약 30 nm/sec의 속도로 기판을 타겟 좌우로 swing 하면서 동적 증착 공정을 한 AZO 박막의 columnar structure가 정적 증착일 때와 다른 형태의 zigzag-type columnar structure가 형성되었다. 투명전도막의 가장 중요한 특성인 비저항과 투과도가 동적 증착 공정일 때의 박막과 정적 증착 공정일 때의 박막이 각각 $2.5{\times}10^{-3}{\Omega}{\cdot}cm$, 78.5%와 $1.65{\times}10^{-3}{\Omega}{\cdot}cm$, 83.9% 였다. 이렇게 성장하는 막의 구조 형태에 따라 달라지는 특성 변화는 양산하는 현장에서 매우 중요한 것이며, 동적 증착 공정에서의 박막 특성 개선에 정적 증착 공정과는 다른 방법의 연구가 필요할 것이다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.05a
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• pp.170-170
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• 2004

박막의 접착강도를 측정하기 위하여 수직력과 수평력을 동시에 측정할 수 있는 0.1∼100 N 용량의 2축 로드셀에 기반을 둔 스크레치 테스터를 개발하였다. 반도체용 Si wafer 기판 위에 Au나 Al 등의 금속이 관은 박막으로 증착된 제품을 table에 고정시킨 후, 2축 로드셀(x, z)이 장착된 하중센서의 선단에 Diamond Tip을 장착하여 기판과 박막에 하중(z-axis)을 증가시키면서 동시에 wafer를 x축 방향으로 이동시킨다. 이런 방식으로 시료의 표면을 긁으면 박막이 벗겨져 나가 Diamond Tip이 기판에 닿을 때 서로 다른 경도차에 의해 진동이 발생하게 되고, 이 진동을 Acoustic Emission 센서에서 감지하여 Crack 발생 시점의 Load와 Stroke를 찾아내게 된다.(중략)

• Journal of the Korean Vacuum Society
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• v.11 no.2
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• pp.103-107
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• 2002

Metal/ferroelectric/semiconductor field effect transistors(MFSFET′s) with various gate electrodes, that are aluminum, platinum and poly-Si, using rapid thermal annealed $LiNbO_3$/Si(100) structures were fabricated and the properties of the FET′s have been discussed. The drain current of the "on" state of FET with Pt electrode was more than 3 orders of magnitude larger than the "off" state current at the same "read" gate voltage of 1.5 V, which means the memory operation of the MFSFET. A write voltage as low as about $\pm$4 V, which is applicable to low power integrated circuits, was used for polarization reversal. The retention properties of the FET using Al electrode were quite good up to about $10^3$ s and using Pt electrode remained almost the same value of its initial value over 2 days at room temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.428-431
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• 2002

Recently, the study on development of electrical and electronic device is done to get miniature, high degrees of integration and efficiency by using inorganic materials. the study of Langmuir-Boldgett(LB) method that uses organic materials because of the limitation for the ultrasmall size. The structure of MIM(Metal-Insulator-Metal) device is Cr-Au/ PBLG/ Al. the number of accumulated layers are 1, 3, 5, 7, 9. The I-V characteristic of the device is measured from 0[V] to 2[V] and the characteristic of current-time of the devices. We have investigated the capacitance because PBLG system have a accumulated layers the maximum value of measured current is increased as the number of accumulated layers are decreased. The capacitor properties of a thin film is better as the distance between electrodes is smaller. The results have shown the insulating materials and could control the conductivity by accumulated layers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.385-386
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• 2008

This paper reports the design of the ultra low power consumption microhotplates for high temperatures. The microhotplates consisting of a platinum-based heating element on AlN/poly 3C-SiC layers were designed. The microhotplate is a $600\times600{\mu}m^2$ square shaped membrane made of $1{\mu}m$ thick ploy 3C-SiC suspended by four legs. The microhotplate was compared with $Si_3N_4/SiO_2/Si_3N_4$(NON) structure microhotplate by COMSOL simulation system. Thermal uniformity, power consumption and thermal characterizations of microhotplates based on 3C-SiC thin film are better than microhotplates with NON structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.15-15
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• 2008

산화물 반도체가 실리콘 기반의 기술을 대체할 새로운 기술로써 주목을 받기 시작하면서, 산화아연을 이용한 박막트랜지스터가 많은 주목을 받고 있다. 여기에 기존의 $SiO_2$를 대체할 새로운 High-k Material에 대한 연구 또한 진행되고 있는데, 이들의 가장 큰 문제점중 하나는 Interface Charge Trap이며, 그에 따른 결과로 히스테리시스 특성이 나타나게 되고, 이는 소자의 신뢰성에 큰 걸림돌이 되고 있다. 이번 연구에서는, High-k Material들 중의 하나인, $HfO_2$를 게이트 절연막으로 사용함에 있어서 Interface Charge Trap이 발생하는 문제를 해결하고자 하며, Low-k Material중에서 비교적 높은 유전상수를 갖는 $Al_2O_3$를 Buffer Layer로써 사용하여, 히스테리시스 특성을 향상 시켰다.