• 보존과학연구
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• s.20
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• pp.81-90
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• 1999

We performed the non-destructive analysis of objects excavated at the Tomb of Mich’un-ri in Ch’ung-won. We analysed components using of Energy Dispersive X-Ray Micro-Fluorescence Analyzer. Glass bead inlaid with silver was classified as K2O-CaO-SiO2 type of glass. Purity of silver inlaid in the surface was verified above 97%.All small ear-ring were made by rolling up gold broad to a bronze wick. The composition ratio of Au : Ag has significantly higher 87 : 11 than bigear-ring. As a result of composition analysis of a welded part with big ear-ring, it contained the more Cu, Hg contents and the less Au, Ag contents than the surface of big ear-ring.

• Proceedings of the Korean Vacuum Society Conference
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• 1995.02a
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• pp.057-58
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• 1995

극소전자 디바이스의 고집적화에 의해 박막배선의 선폭은 0.5$mu extrm{m}$ 이하로 축소되고 있고 상대적으로 높은 전류밀도가 흐르게 된다. 높은 전류밀도하에서는 현재 일반적으로 사용되고 있는 Al을 기본으로 하는 박막배선에서의 electromigration에 의한 결함 발생 그리고 비교적 낮은 전기전도도가 심각한 문제점으로 제기된다. 본 연구에서는 Al과 고전기전도도 물질인 Ag, Cu, 그리고 Au 박막배선에 대해 electromigration에 대한 저항성, 즉 activation energy를 측정 비교함으로써 차세대 극소전자 디바이스를 위한 박막배선재료로서의 가능성을 알아보고자 한다. Electromigration test 및 activation energy를 구하기 위해 순수 Ag, Cu, Al, Au 박막배선을 0.05$\mu\textrm{m}$ 두께, 100$\mu\textrm{m}$ 선폭, 그리고 5000$\mu\textrm{m}$ 길이로 SiO2 열산화막 처리된 pp-Si(100) 기판 위에 진공 증착시켰다. 가속화 실험을 위해 인가된 d.c. 전류밀도는 2$\times$106A/$ extrm{cm}^2$ 이었고, Al과 Au에서는 6$\times$106A/$\textrm{cm}^2$이었다. 실온에서 24$0^{\circ}C$까지의 온도범위에서 d.c.인가후의 저항변화를 측정하여 Median-Time-to-Failure(MTF)를 구한 후 Black 방정식을 이용하여 activation energy를 측정하였다. Activation energy는 Cu가 1.34eV로서 가장 높게 나타났고 Au가 1.01eV, Al이 0.66eV, Ag가 0.29eV의 순으로 측정되었다. 따라서 Cu와 Au 박막배선의 경우 Al보다 electromigration에 대한 저항력이 강한 고활성화에너지 특성을 갖는 고전기전도도 재료로서 차세대 극소전자 디바이스를 위한 대체 박막배선재료로서의 가능성을 보인다.

• Korean Journal of Materials Research
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• v.34 no.7
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• pp.370-376
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• 2024

In this study, we report significant improvements in lithium-ion battery anodes cost and performance, by fabricating nano porous silicon (Si) particles from Si wafer sludge using the metal-assisted chemical etching (MACE) process. To solve the problem of volume expansion of Si during alloying/de-alloying with lithium ions, a layer was formed through nitric acid treatment, and Ag particles were removed at the same time. This layer acts as a core-shell structure that suppresses Si volume expansion. Additionally, the specific surface area of Si increased by controlling the etching time, which corresponds to the volume expansion of Si, showing a synergistic effect with the core-shell. This development not only contributes to the development of high-capacity anode materials, but also highlights the possibility of reducing manufacturing costs by utilizing waste Si wafer sludge. In addition, this method enhances the capacity retention rate of lithium-ion batteries by up to 38 %, marking a significant step forward in performance improvements.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.4
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• pp.348-352
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• 2022

Resistive switching behaviors of a co-sputtered zinc silicate thin film (ZnO and SiO₂ targets) have been investigated. We fabricated an Ag/ZnSiO_x/highly doped n-type Si substrate device by using an RF magnetron sputter system. X-ray diffraction pattern (XRD) indicated that the Zn₂SiO₄ was formed by a post annealing process. A unique morphology was observed by scanning electron microscope (SEM) and atomic force microscope (AFM). As a result of annealing process, 50 nm sized nano clusters were formed spontaneously in 200~300 nm sized grains. The device showed a unipolar resistive switching process. The average value of the ratio of the resistance change between the high resistance state (HRS) and the low resistance state (LRS) was about 106 when the readout voltage (0.5 V) was achieved. Resistance ratio is not degraded during 50 switching cycles. The conduction mechanisms were explained by using Ohmic conduction for the LRS and Schottky emission for the HRS.

• Proceedings of the Korean Vacuum Society Conference
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• 2008.02a
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• pp.127-127
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• 2008

• Transactions of Materials Processing
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• v.15 no.3 s.84
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• pp.213-219
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• 2006

To improve the strength of glass is being studied in order to contribute to weight saving of flat panel displays. Generally, the strength achieved of glass-ceramics is higher as is the fracture toughness by the formation of a heterogeneous phase inside glass. In this study, Ag-doped $45SiO_2-24CaO-24Na_2O-4P_2O_5\;and\;70SiO_2-10CaO-24Na_2O-10TiO_2$ glasses were irradiated to strengthen by crystallization using femto-second laser pulse. XRD, Nano-indenter and SEM etc., irradiation of laser pulse without heat-treated samples was analyzed. Samples irradiated by laser had higher value($4.4{\sim}4.56^*10-3Pa$) of elastic modulus which related with strength of glass than values heat-treated samples and these are $1.2{\sim}1.5$ times higher values than them of mother glass. This process can be applicable to the strengthening of thinner glass plate, and it has an advantage over traditional heat-treatment and ion-exchange method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.251-254
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• 2001

This paper describes an efficiency improvement of buried contact solar cell (BSCS) with a structure of MgF$_2$/CeO$_2$/Ag/Cu/Ni grid/n$^{+}$ emitter/p-type Si base/p$^{+}$/Al. Theoretical and experimental investigations were performed on a double layer antireflection (DLAR) coating of MgF$_2$/CeO$_2$. We investigated CeO$_2$ films as an AR layer because they have a proper refractive index of 2.46 and demonstrate the same lattice constant as Si substrate. An optimized DLAR coating shewed a reflectance as low as 2.04 % in the wavelengths ranged from 0.4 ${\mu}{\textrm}{m}$ to 1.1 ${\mu}{\textrm}{m}$. BCSC cell efficiency was improved from 16.2 % without any AR coating to 19.9 % by employing DLAR coatings. Further details on MgF$_2$/CeO$_2$ DLAR coatings on the BCSC cells are presented in this paper.per.

• Journal of Electrical Engineering and information Science
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• v.3 no.1
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• pp.68-72
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• 1998

The photomachinable glass-ceramics of Ag and CeO2 doped Li203-SiO2 (LAS)glass system was investigated as a function of UV irradiation time. After the expose and the non-exposed samples were heated, they went under crystalline phase with DTA, SEM, TEM and XRD of normal/high temperature. In this work, crystalline phases, microstructure and dielectric properties were studied under the various time of UV irradiation and heat treatment.

• Korean Journal of Materials Research
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• v.24 no.12
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• pp.694-699
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• 2014

We report the chemical vapor deposition growth characteristics of graphene on various catalytic metal substrates such as Ni, Fe, Ag, Au, and Pt. 50-nm-thick metal films were deposited on $SiO_2/Si$ substrates using dc magnetron sputtering. Graphene was synthesized on the metal/$SiO_2$/Si substrates with $CH_4$ gas (1 SCCM) diluted in mixed gases of 10% $H_2$ and 90 % Ar (99 SCCM) using inductively-coupled plasma chemical vapor deposition (ICP-CVD). The highest quality of graphene film was achieved on Ni and Fe substrates at $900^{\circ}C$ and 500 W of ICP power. Ni substrate seemed to be the best catalytic material among the tested materials for graphene growth because it required the lowest growth temperature ($600^{\circ}C$) as well as showing a low ICP power of 200W. Graphene films were successfully grown on Ag, Au, and Pt substrates as well. Graphene was formed on Pt substrate within 2 sec, while graphene film was achieved on Ni substrate over a period of 5 min of growth. These results can be understood as showing the direct CVD growth of graphene with a highly efficient catalytic reaction on the Pt surface.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.49-53
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• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.