• Journal of the Korean Statistical Society
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• v.33 no.4
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• pp.401-410
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• 2004

We address the problem of parameter estimation in multivariate distributions under ignorable non-monotone missing data. The factoring likelihood method for monotone missing data, termed by Rubin (1974), is extended to a more general case of non-monotone missing data. The proposed method is algebraically equivalent to the Newton-Raphson method for the observed likelihood, but avoids the burden of computing the first and the second partial derivatives of the observed likelihood. Instead, the maximum likelihood estimates and their information matrices for each partition of the data set are computed separately and combined naturally using the generalized least squares method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.46-56
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• 1991

In this paper, 16word X 8bit Content Addressable and Reentrant Memory(CARM) is described. This device has 4 operation modes(read, write, match, reentrant). The read and write operation of CARM is like that of static RAM, CARM has the reentrant mode operation where the on chip garbage collection is accomplished conditionally. Thus function can be used for high speed matching unit of dynamic data flow computer. And CARM also can encode matching address sequentially according to therir priority. CARM consists of 8 blocks(CAM cell, Sequential Address Encoder(S.A.E). Reentrant operation. Read/Write control circuit, Data/Mask Register, Sense Amplifier, Encoder. Decoder). Designed DARM can be used in data flow computer, pattern, inspection, table look-up, image processing. The simulation is performed using the QUICKSIM logic simulator and Pspice circuit simulator. Having hierarchical structure, the layout was done using the 3{\;}\mu\textrm{m} n well CMOS technology of the ETRI design rule.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.68-75
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• 2016

As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.

• The Journal of Korean Society for School & Community Health Education
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• v.25 no.1
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• pp.29-41
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• 2024

Objectives: This study used an efficient data mining algorithm to explore association rules between the lifestyle risk behaviors and multimorbidity (having more than one chronic disease) in Korean adults. Methods: We used data from the 8th Korean National Health and Nutrition Examination Survey(2019-2020) for 7,609 adults aged ≥19 years. This study was undertaken where 6 lifestyle risk behaviors and 11 morbidities were analyzed using R and Rstudio for the ARM. Results: Among 117 association rules, combinations of hypertension, dyslipidemia and diabetes, hypertension were important role in inadequate sleep, physical inactivity and inadequate weight. Conclusion: The findings of this study are significant because they demonstrate the importance of lifestyle risk factors and the role of multiple chronic diseases using big data analytics such as association rule mining. We recommend developing selective and focused health education programs, such as exercise programs to address physical inactivity, dietary interventions to address inadequate weight, and mental health education programs to address inadequate sleep.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.

• Journal of the Korean Data and Information Science Society
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• v.15 no.3
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• pp.605-616
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• 2004

In this paper we consider the proportional hazard models for survival analysis in the microarray data. For a given vector of response values and gene expressions (covariates), we address the issue of how to reduce the dimension by selecting the significant genes. In our approach, rather than fixing the number of selected genes, we will assign a prior distribution to this number. To implement our methodology, we use a Markov Chain Monte Carlo (MCMC) method.

• Genomics & Informatics
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• v.5 no.2
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• pp.83-87
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• 2007

The analysis of DNA microarray data is a rapidly evolving area of bioinformatics, and various types of microarray are emerging as some of the most exciting technologies for use in biological and clinical research. In recent years, microarray technology has been utilized in various applications such as the profiling of mRNAs, assessment of DNA copy number, genotyping, and detection of methylated sequences. However, the analysis of these heterogeneous microarray platform experiments does not need to be performed separately. Rather, these platforms can be co-analyzed in combination, for cross-validation. There are a number of separate laboratory information management systems (LIMS) that individually address some of the needs for each platform. However, to our knowledge there are no unified LIMS systems capable of organizing all of the information regarding multi-platform microarray experiments, while additionally integrating this information with tools to perform the analysis. In order to address these requirements, we developed a web-based LIMS system that provides an integrated framework for storing and analyzing microarray information generated by the various platforms. This system enables an easy integration of modules that transform, analyze and/or visualize multi-platform microarray data.

• Korean Journal of Construction Engineering and Management
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• v.24 no.3
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• pp.3-11
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• 2023

This research examines the need for a quantitative and objective method of calculating baseline productivity in the construction industry, which is known for its high volatility in performance and productivity. The existing literature's baseline productivity calculation methods rely heavily on subjective criteria, limiting their effectiveness. Additionally, data collection methods such as the "Five-minute Rating" are costly and time-consuming, making it challenging to collect detailed data at construction sites. To address these issues, this study proposes an objective baseline calculation method using unimpacted productivity BP, a work check sheet to systematically record detailed data, and a data collection and utilization process that minimizes cost and time requirements. This paper also suggests using unimpacted productivity BP and comparative analysis to address the objectivity and reliability issues of existing baseline productivity calculation methods.

• Journal of Digital Contents Society
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• v.15 no.6
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• pp.663-673
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• 2014

The WBAN technology means a short distance wireless network which provides each device interactive communication by connecting devices inside and outside of body. Standardization on the physical layer, data link layer, network layer and application layer is in progress by IEEE 802.15.6 TG BAN. Wireless body area network is usually configured in energy efficient using sensor and zigbee device due to the power limitation and the characteristics of human body. Wireless sensor network consist of sensor field and sink node. Sensor field are composed a lot of sensor node and sink node collect sensing data. Wireless sensor network has capacity of the self constitution by protocol where placed in large area without fixed position. In this paper, we proposed the efficient addressing scheme for improving the performance of routing algorithm by using ZigBee in WBAN environment. A distributed address allocation scheme used an existing algorithm that has wasted in address space. Therefore proposing x, y and z coordinate axes from divided address space of 16 bit to solve this problems. Each node was reduced not only bitwise but also multi hop using the coordinate axes while routing than Cskip algorithm. I compared the performance between the standard and the proposed mechanism through the numerical analysis. Simulation verified performance about decrease averaging multi hop count that compare proposing algorithm and another. The numerical analysis results show that proposed algorithm reduced the multi hop better than ZigBee distributed address assignment

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.4
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• pp.22-27
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• 2004

The gas discharge AND gate which have been newly proposed is applied to three electrode surface discharge AC PDP. The address discharge characteristics by the DC-AC floating discharge by which Y electrode is made floating electrode is analyzed The address discharge can be begun by using the floating discharge from the experiment result Moreover, the display discharge can be sustained. The DC priming discharge that the floating discharge is matched to timing is generated in a supplementary electrode. As a result, space charge is supplied enough to the space of the floating discharge and the data voltage is lowered up to l00(V). Driving method to use this DC-AC floating discharge is able to obtain the address operation margin of l00(V).