• Journal of Power Electronics
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• 제15권3호
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• pp.587-601
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• 2015

A high step-up dc-dc converter is proposed for photovoltaic power systems in this paper. The proposed converter consists of an input current doubler, a symmetrical switched-capacitor doubler and an active-clamp circuit. The input current doubler minimizes the input current ripple. The symmetrical switched-capacitor doubler is composed of two symmetrical quasi-resonant switched-capacitor circuits, which share the leakage inductance of the transformer as a resonant inductor. The rectifier diodes (switched-capacitor circuit) are turned off at the zero current switching (ZCS) condition, so that the reverse-recovery problem of the diodes is removed. In addition, the symmetrical structure results in an output voltage ripple reduction because the voltage ripples of the charge/pump capacitors cancel each other out. Meanwhile, the voltage stress of the rectifier diodes is clamped at half of the output voltage. In addition, the active-clamp circuit clamps the voltage surges of the switches and recycles the energy of the transformer leakage inductance. Furthermore, pulse-width modulation plus phase angle shift (PPAS) is employed to control the output voltage. The operation principle of the converter is analyzed and experimental results obtained from a 400W prototype are presented to validate the performance of the proposed converter.

• Journal of Power Electronics
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• 제14권5호
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• pp.834-841
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• 2014

This paper proposes new active switched-capacitor and switched-inductor Z-source inverter (ASC/SL-ZSI) topologies, which can provide a higher boost ability with a small shoot-through time. The proposed ASC/SL-ZSIs inherit all of the advantages of the classical ZSI, and have a stronger voltage boost inversion ability when compared with the classical ZSI. Thus, the output ac voltage quality is significantly improved. In addition, more cells can be cascaded in the impedance network in order to obtain a very high boost ability. The proposed topologies can be applied to photovoltaic or fuel-cell generation systems with low-voltage renewal sources due to their wide range of obtainable voltages. Both simulations and the experimental results are carried out in order to verify performance of the proposed topologies.

• 한국통신학회논문지
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• 제7권1호
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• pp.10-17
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• 1982

최근 switched capacitors 및 고정 capacitors와 능동소자를 利用한 analong 여파기 실현에 큰 관심을 갖게 되었다. Switched capacitor는 저항에 비해 온도특성 및 선형특성이 양호할 뿐 아니라 Si chip 면적이 훨씬 적게 소요되고 MOS기술에 의해 완전 IC화가 가능하다. 본 논문에서는 저항과 switched capacitor를 사용해 Gyrator 여파기내의 모든 저항을 switched capacitor로 대친시킬 SC-Gyrator 여파기를 실현했다. 실험결과 Gyrator여파기와 SC-Gyrator 여파기의 특성이 만족할 만큼 일치함을 확인했다.

• 한국통신학회논문지
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• 제4권1호
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• pp.25-31
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• 1979

All the resitors in the active RC filter networks can be relplaced by the switched capacitors. Therefore, An SC filter circuit can be fully integrated using MOS technology. A switched capacitor is much better than a resistor in temperature and linearity characteristics, and the former can be fabricated on the much smaller area then the latter. In this paper, It is given the generalized disign method of the active SC filter from the active RC filter using Bilinear Z-transformation. By SC filtering Techniques using Bilinear Z-transform, It enalbes us to realize the FDNR and Gyrator filters, which could not be realized in the exsisting designs, and it permits the processing of signals at much higher frequenies that many previous designs do. Experiments show that the response of the SC active filter is similiar to that of its prototype active RC filter.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.625-631
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• 2014

We propose a compact power-on reset circuit consisting of a switched capacitor, a capacitor, and a Schmitt trigger inverter. A switched capacitor working with a clock signal charges the capacitor. Thus, the voltage across the capacitor is increased toward the supply voltage. The circuit provides a reset pulse until the voltage across the capacitor reaches the high threshold voltage of the Schmitt trigger inverter. The proposed circuit is simple, compact, has no static power consumption, and works for a wide range of power-on rising times. Furthermore, the clock signal is available while the reset pulse is activated. The proposed circuit works for up to 6 s of power-on rising time, and occupies a $60{\times}30{\mu}m^2$ active area.

• 대한전기학회논문지
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• 제33권12호
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• pp.472-479
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• 1984

In order to realize the simple and economic 3rd order LPF using switched-capacitor(SC), we proposed the 3rd order RC LPF using a OP amplifier and realized the 3rd order SC LPF by replacing all the resistors in the RC LPF to SC. The frequency response of SC LPF was compared with the that of RC LPF. As a result, it was found that the response of realized SC LPF is almost similar to that of RC LPF.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 추계학술대회 논문집
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• pp.105-106
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• 2013

This paper proposes a new topology with active switched-capacitor and switched-inductor impedance network, which can obtain a high boost factor with small shoot-through time. The proposed topology uses an active switched capacitor and switched-inductor impedance network in order to couple the main circuit and input dc source for boosting the output voltage. The proposed topology contains all advantages of the classical Z-source inverter. Comparing with other topologies, the proposed topology uses lesser component and the voltage boost inversion ability significantly increases. The theoretical analysis, pulse width modulation control strategies, and a comparison with classical ZSI have been given in this paper. Both simulation and experimental results will be presented to verify the advantages of the proposed topology.

• 전기학회논문지
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• 제59권10호
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• pp.1839-1844
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• 2010

A power management controller circuit with switched capacitor mode down regulator and battery charger block for semi-active RFID tags was proposed and fabricated. The main purposes of the proposed switched capacitor mode down regulator and battery charger block are to reduce standby current and to provide a self-controlled thin film battery charger by detecting the received RF power, respectively. Fabricated chip area is $360,000{\mu}m^2$ and measured standby current was about $1.3{\mu}A$. To further reduction of standby current, a wake-up circuit has to be included in the power management controller.

• Journal of Power Electronics
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• 제19권1호
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• pp.1-10
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• 2019

Current imbalance is the main factor affecting the lifespan of light-emitting diode (LED) lighting systems and is generally solved by active or passive approaches. Given many new lighting applications, independent control is particularly important in achieving different levels of luminance. Existing passive and active approaches have their own limitations in current sharing and independent control, which bring new challenges to the design of LED drivers. In this work, a multichannel resonant converter based on switched-capacitor control (SCC) is proposed for solving this challenge. In the resonant network of the upper and lower half-bridges, SCC is used instead of fixed capacitance. Then, the individual current of the LED array is obtained through regulation of the effective capacitance of the SCC under a fixed switching frequency. In this manner, the complexity of the control unit of the circuit and the precision of the multichannel outputs are further improved. Finally, the superior performance of the proposed LED driver is verified by simulations and a 4-channel experimental prototype with a rated output power of 20 W.

• 전기학회논문지P
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• 제52권4호
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• pp.148-153
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• 2003

In this paper, the low voltage 3V Sigma-Delta Digital Analog Converter(DAC) is designed for using in the transmitter of ADSL analog front-end. We have developed the CMOS DAC according to ANSI T1.413-2(DMT) standard specifications of the chip. The designed 4th-order DAC is composed of three block which are 1-bit DAC, 1st-order Switched-Capacitor filter and analog active 2nd-order Resistor-Capacitor(RC) filter. The HSPICE simulation of the designed DAC showing 65db SNR, is connected with 1.1MHz continuous lowpass filter. And also, we have performed the circuits verification and layout verification(ERC, DRC, LVS) followed by fabrication using TSMC 2-poly 5-metal p-substrate CMOS $0.35{\mu}m$ processing parameter. Finally, the chip testing has been performed and presented in the results.