• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.176-186
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• 1996

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.28-36
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• 2002

As cross-coupling capacitance generated in transmission line has been an important issue in VLSI world, a couple of ATPG algorithms has been proposed. However they were studied only for a simple single-line effect problem, so it cost so much time for an unsatisfying test generation efficiency. In this paper, we studied a noise model for multiple affected lines and generated test patterns in a short time. This paper proposes a crosstalk model affected by multiple tranmission lines and implemented an ATPG algorithm for detection of crosstalk noise faults. We modeled the crosstalk noise by multiple transmission line and made a truth table for this. We implemented an ATPG algorithm based on PODEM and revealed the results.

• Plant Breeding and Biotechnology
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• v.5 no.3
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• pp.237-242
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• 2017

AT-hook proteins of plant have shown to be involved in growth and development through the modification of chromatin architecture to co-regulate transcription of genes. Recently, many genes encoding AT-hook protein have been identified and their involvement in senescence delay is investigated. In this study, soybean transgenic plants overexpressing chromatin architecture-controlling ATPG7 gene was produced by Agrobacterium-mediated transformation and investigated for the positive effect on the important agronomic traits mainly focusing on yield-related components. A total of 27 transgenic soybean plants were produced from about 400 explants. $T_1$ seeds were harvested from all transgenic plants. In the analysis of genomic DNAs from soybean transformants, ATPG7 and Bar fragments were amplified as expected, 975 bp and 408 bp in size, respectively. And also exact gene expression was confirmed by reverse transcriptase-PCR (RT-PCR) from transgenic line #6, #7 and #8. In a field evaluation of yield components of ATPG7 transgenic plants ($T_3$), higher plant height, more of pod number and greater average total seed weight were observed with statistical significance. The results of this study indicate that the introduction of ATPG7 gene in soybean may have the positive effect on yield components.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.792-793
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• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.558-565
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• 2000

While research of ATPG(automatic test pattern generation) for combinational circuits almost reaches a satisfiable level, one for sequential circuits still requires more research. In this paper, we propose new algorithm for sequential ATPG based on state information learning. By efficiently storing the information of the state searched during the process of test pattern generation and using the state information that has been already stored, test pattern generation becomes more efficient in time, fault coverage, and the number of test patterns. Through some experiments with ISCAS '89 benchmark circuits, the efficiency of the proposed method is shown.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.71-79
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• 1993

This paper proposes a new test pattern generation methodology for combinational logic circuits using neural networks based on a modular structure. The CUT (Circuit Under Test) is described in our gate level hardware description language. By conferring neural database, the CUT is compiled to an ATPG (Automatic Test Pattern Generation) neural network. Each logic gate in CUT is represented as a discrete Hopfield network. Such a neual network is called a gate module in this paper. All the gate modules for a CUT form an ATPG neural network by connecting each module through message passing paths by which the states of modules are transferred to their adjacent modules. A fault is injected by setting the activation values of some neurons at given values and by invalidating connections between some gate modules. A test pattern for an injected fault is obtained when all gate modules in the ATPG neural network are stabilized through evolution and mutual interactions. The proposed methodology is efficient for test generation, known to be NP-complete, through its massive paralelism. Some results on combinational logic circuits confirm the feasibility of the proposed methodology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.803-806
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• 2007

Since the different characteristics from the PRNG (Pseudo Random Number Generator) or various deterministic devices such as arithmetic processing units, new concepts and test methods should be suggested in order to test TRNG (Ture Random Number Generator). Deterministic devices can be covered by ATPG (Automatic Test Pattern Generation), which uses patterns generated by cyclic shift registers due to its hardware oriented characteristics, pure random numbers are not possibly tested by automatic test pattern generation due to its analog-oriented characteristics. In this paper, we studied and analyzed a hardware/software combined test method named Diehard test, in which we apply continuous pattern variation to check the statistics. We also point out the considerations when making random number tests.

• The Magazine of the IEIE
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• v.20 no.11
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• pp.75-84
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• 1993

• 전기의세계
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• v.40 no.6
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• pp.30-37
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• 1991

본 고에서는 먼저 chip 기술의 발전 경향을 살펴본 후, 기존 ATPG의 개념과 기법을 알아보고 DL의 개념 및 용도를 소개한 후 DFT의 세가지 주요기법:Ad-hoc기법, Structured기법 및 self-test 기법에 대하여 기술하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.145-153
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• 2001

As combinational ATPG algorithms achieve effectively 100% fault coverage, reducing the length of test set without loosing its fault coverage becomes a challenging work. The new approach is based on the independent and the compatible relationships between faults. For more compact test set, the size of compatible fault set must be maximized, thus this algorithm generates fault-pattern pairs, and a fault-pattern pair tree structure using the independent and the compatible relationships between faults. With the fault-pattern pair tree structure, a compact test set effectively generated. The experimental results for ISCAS 85 and 89 benchmark circuits demonstrate the effectiveness of the proposed method.