• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06e
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• pp.223-226
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• 1998

In the Input Buffer Switch using the intial stage FIFO memory structure, It has pointed the Throughput limitation to the percent of 58.6 due to HOL(Head of Line) blocking in the DBP(Dedicated Buffer with Pointer) method, During that time, To overcome these problems, The prior papers have proposed the complicated Arbitration algorithms and Non-FIFO memory structures. and These showed the improved Throughput. But, Now, To design high speed ATM Switch which need to the tens of Giga bit/s or the tens of Tera bit/s. It has more difficulty in proceeding the priority of majority and the complicated Cell Scheduling, because of the problem in operating the control speed of the ratio of N to scanning each port and scheduling the Cell. In this paper, To overcome these problems, We could show more the improved performance than the existing DBP Window policy to design high speed ATM Switch.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.264-267
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• 2002

This paper presents the design of a pipelined virtual output queue routing engine for an advanced input-queued ATM switch, which has a serial cross bar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array (FPGA) chip with a 77MHz operating frequency, 16$\times$16 switch size, and 2.5Gbps/port speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.629-642
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• 1996

ATM switch handles the traffic for a wide range of appliations with different QOS(Quality-of-Service) requirements. In ATM switch, the priority control mechanism is needed to improve effectively the required QOS requirements. In this paper, we propose a priority control mechanism using the cell transfer ratio type and discard threshold in order to archive the cell loss probability requirement and the delay requirement of each service class. The service classes of our concern are the service class with high time priority(class 1) and the service class with high loss priority control mechanism, cells for two kind of service classes are stored and processed within one buffer. In case cells are stored in the buffer, cells for class 2 are allocated in the stored and processed within one buffer. In case cells are stored in the buffer, cells for class 2 are allocated in the shole range of the buffer and cells for class 1 are allocated up to discard threshold of the buffer. In case cells in the buffer are transmitted, one cell for class 1 is transmitted whenever the maximum K cells for class 2 are transmitted consecutively. We analyze the time delay and the loss probability for each class of traffic using Markov chain. The results show that the characteristics of the mean cell delay about cells for class 1 becomes better and that of the cell loss probability about cells for class 2 becomes better by selecting properly discard threshold of the buffer and the cell transfer ratio according to the condition of input traffic.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.8
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• pp.30-41
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• 2001

In this paper, the architecture of Dynamic GSMP V3(General Switch Management Protocol Version 3), an open interface protocol with resource management functions for efficient IP service on ATM over MPLS, is proposed and implemented in hardware. And we compare and analyze the proposed GSMP with the GSMP under standardization process in terms of CLR (Cell Loss Rate). We design the Slave block of the Dynamic GSMP V3 using SAM-SUNG SoG $0.5{\mu}m$ process, which performs functions for switch connection control in the ATM Switch. In order to compare difference performanaces between the proposed method and the conventional one, we conducts simulations using the minimum buffer search algorithm with random cell generation. The exponential results show that the proposed method leads to performance enhancement in CLR.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.48-50
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• 1998

메시지에 기반을 둔 다중컴퓨터는 프로세서들 간에 고속통신을 위한 연결 망을 요구한다. ATM 스위치는 대규모의 다중컴퓨터를 구성하기에 유리한 접근 방식을 제공하며, 낮은 지연시간과 고성능을 제공하는 특성을 가진다. 본 논문은 고속 ATM 스위치를 통한 프로세서들간의 정보를 송신/수신하는 셀 라우터를 설명한다. 고속 ATM 스위치를 효율적으로 사용하기 위하여, 본 논문은 다중화와 역 다중화를 가지고 계층적 구조를 제안한다. 일반 연결 망에서 라우팅을 위해 착신주소를 가지는 기본단위는 메시지이지만, ATM 망에서는 셀이라고 부르는 고정된 크기의 프레임이 기본단위이다. 셀은 VPI와 VCI를 가지며, 이는 송신/수신 프로세서의 구별자로서 사용된다 결론적으로 제안한 고속 셀 라우터와 계층적 구조는 메시지 전송지연의 관점에서 이점을 가질 수 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.340-343
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• 1998

사설 ATM 스위치에서 인터넷이나 프레임 릴레이 등과 같은 이 기종 망 접속 장비들을 접속하기 위한 망 인터워킹 서비스를 수행하기 위하여 이들의 신호 및 연결 제어를 수행하기 위한 PSA(Proxy Signaling Agent)의 기능을 정의하고, PSA 신호 기능을 수행하기 위한 사설 ATM 스위치에서 수용 가능한 두 가지의 하드웨어 구조를 제안한다. 그리고 이 제안된 하드웨어 구조 상에서 PSA 기능을 수행하기 위한 신호 메시지 전달 방법을 알아보고, non-ATM 망 상의 서비스 이용자를 수용하기 위하여 PSA 기능을 수행하기 위한 ATM 주소 번역 기능, 서비스 대역 폭 할당 및 준비, 트래픽과 QoS 협상 등을 수행하는 PSA를 이용한 호 연결 설정 절차에 대하여 자세히 기술하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1200-1207
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• 1996

The paper presents and analyzes two efficient burst-level bandwidth reservation protocols for multi-hop ATM Local Area Networks. With the tell-and-wait (TNW) protocol and the tell-and-go (TNG) protocol[6], a negative acknowledgmen(NACK) message representing the bandwidth starvation on a switch on the source-destnation path can be always sent by a destination. We note that the protocols waste more bandwidth as the round-trip delay increases, since the switches on the path must reserve the bandwidth until the NACK will arrive. Based on this pitfall, the proposed protocols allow and ATM node, rather than a destination node to send a NACK. This allowance can save the needless bandwidth wastage. Using the thinned load approximation method, we show the proposed protocols have good performance and practical simplicity. Thus, the proposed protocols may be candidates for the ABR service in multi-hop ATM LANs and ATM WANs.

• IE interfaces
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• v.9 no.3
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• pp.120-142
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• 1996

Asynchronous Transfer Mode (ATM) is considered to be the most promising transfer technique for BISDN due to its efficiency and flexibility. Queueing theory has been playing a very important role in performance evaluation of ATM for the past few years. This paper is composed of two parts. The first part is concerned with the several basic concepts of ATM. The second part surveys queueing approaches in ATM performance evaluation. It deals with stochastic models which have been proposed for the three basic categories of traffic sources (voice, data, video), various queueing models for statistical multiplexer and switch, and priority strategies for buffer control schemes.

• Journal of the Korea Society of Computer and Information
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• v.3 no.4
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• pp.132-138
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• 1998

A network of Asynchronous Transfer Mode (ATM) will be required to carry the traffics(CVR, VBR, UBR, ABR) generated by a wide range of services. The traffic ABR uses the remined space of the CBR/VBR traffics bandwith. The Rate-based, the Credit-based, and the mixed method that are implementing the control loop of ABR traffic service is on study. In this paper, a new algorithm that can be considered in ATM and effectively manage ABR traffic using VS/VD method and EPRCA algorithm is proposed on the switch of the Rate-based method

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1995.10a
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• pp.306-309
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• 1995