• The Journal of the Korea Contents Association
• /
• v.5 no.3
• /
• pp.217-225
• /
• 2005

Currently the research on input-queued ATM switches is one of the most active research fields. Many achievements have been made in the research on scheduling algorithms for input-queued ATM switches and also applied in commerce. The scheduling algorithms have the characteristics of improving throughput, satisfying QoS requirements and providing service fairly. In this paper, we studied on an implementation of scheduler which arbitrates the input-queued ATM switches efficiently and swiftly. The proposed scheduler approximately provides $100\%$ throughput for scheduling. The proposed algorithm completes the arbitration for N-port VOQ switch with 4-iterative matching. Also the proposed algorithm has a merit for implementing the scheduling algorithm with 1/2 area compared to that of iSLIP scheduling algorithm which is widely used. The performance of the proposed scheduling algorithm is superior to that of iSLIP in 4-iterative matching.

• The KIPS Transactions:PartC
• /
• v.12C no.1 s.97
• /
• pp.83-96
• /
• 2005

The multichannel switch is an architecture widely used for ATM (Asynchronous Transfer Mode). It is known that the fault tolerant characteristic can be incorporated into the multichannel crossbar switching fabric. For example, if a link belonging to a multichannel group fails, the remaining links can assume responsibility for some of the traffic on the failed link. On the other hand, if a fault occurs in a switching element, it can lead to erroneous routing and sequencing in the multichannel switch. We investigate several fault localization algorithm in multichannel crossbar ATM switches with a view to early fault recovery. The optimal algorithm gives the best performance in terms of time to localization but it is computationally complex which makes it difficult to implement. We develop an on-line algorithm which is computationally more efficient than the optimal one. We evaluate its performance through simulation. The simulation results show that the Performance of the on-line algorithm is only slightly sub-optimal for both random and bursty traffic. There are cases where the proposed on-line algorithm cannot pinpoint down to a single fault. We enumerate those cases and investigate the causes. Finally, a fault recovery algorithm is described which utilizes the information provided by the fault localization algorithm The fault recovery algorithm providesadditionalrowsandcolumnstoallowcellstodetourthefaultyelement.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.8
• /
• pp.1190-1200
• /
• 1993

In this work, the performance of both delay sensitive traffics and loss sensitive traffics of the output buffered ATM switch with priority control mechanisms has been evaluated. We choose the partial buffer sharing mechanism as the loss priority control mechanism and the HOL(Head Of Line) priority control mechanism as the time priority control mechanism. We model loss sensitive traffics with Poisson process and delay sensitive traffics with MMPP. With loss priority control, it is confirmed that loss probability of loss sensitive traffice decreases when the loss priority control mechanism is chosen. With time priority control, it has also been confirmed that mean cell delay of delay sensitive traffics decreases when the HOL priority control mechanism is used. From this analysis, It has been confirmed that the requirements of QOS for both loss sensitive and delay sensitive traffics can be satisfied in the ATM switch by combining both the loss priority control mechanism and the HOL priority control mechanism.

• ETRI Journal
• /
• v.18 no.4
• /
• pp.229-244
• /
• 1997

Realization of the economical, reliable, and efficient ATM interface block becomes an important key to development of the ATM switching system when we consider new issues raised recently. In this paper, we summarize requirements for the ATM interface block and present the UNI (User Network Interface)/NNI (Network Node Interface) architecture to meet these requirements. We also evaluate the performance of the multiplexer adopting the various multiplexing schemes and service disciplines. For ATM UNI/NNI interface technologies, we have developed a new policing device using the priority encoding scheme. It can reduce the decision time for policing significantly. We have also designed a new spacer that can space out the clumped cell stream almost perfectly. This algorithm guarantees more than 99 % conformance to the negotiated peak cell rate. Finally, we propose the interface architecture for accommodation of the ABR (Available Bit Rate) transfer capability. The proposed structure that performs virtual source and virtual destination functions as well as a switch algorithm can efficiently accommodate the ABR service.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 1998.11a
• /
• pp.472-482
• /
• 1998

오늘날의 통신서비스들은 음성이나 데이터 서비스와 같은 전통적인 서비스 뿐만 아니라 비디오 서비스와 같은 대량의 데이터를 전송해야만 하는 멀티미디어 서비스를 포함한다. 이러한 요구를 수용하기 위해서 BISDN(Broadband Integated Digital Network)이 개발되었고 이의 기반 기술로 ATM이 채택되었다. 다양한 멀티미디어 응용들 중에서 VOD(Video On Demand), 화상회의 등은 데이터를 동시에 여러 목적지로 보내는 멀티캐스트 특성이 있다. 그러므로 멀티캐스트 능력은 멀티미디어 통신에서 매우 중요하다. 본 논문에서는 링망을 이용한 병렬 멀티캐스트 패킷스위치(Parallel Multicast Packet Switch with Ring Network: PMRN)에서의 분리된 HOL을 이용한 멀티캐스트 셀 스케줄링 기법을 제안한다. 이 기법은 입력버퍼의 앞단에 멀티캐스트 셀과 유니캐스트 셀을 위한 분리된 HOL을 두고 non-FIFO방식을 사용함으로서 입력버퍼 내에서 전송 가능한 멀티캐스트 셀과 유니캐스트 셀을 동시에 스케쥴링할 수 있도록 하여 입력버퍼 내에서의 지연을 감소시키고 링망과 일대일 연결 네트워크의 이용율을 높이며 스위치의 처리율을 높일 수 있다.

• Journal of the Korea Computer Industry Society
• /
• v.2 no.9
• /
• pp.1163-1174
• /
• 2001

A general goal of the ATM(Asynchronous Transfer Mode) network is to support connections across various networks. ABR service using EPRCA(Enhanced Proportional Rate Control Algorithm) switch controls traffics in ATM network. EPRCA switch, traffic control method uses variation of the ACR(Allowed Cell Rate) to enhance the utilization of the link bandwidth. However, in ABR(Available Bit Rate) service, different treatments are offered according to different RTTs(Round Trip Times) of connections. To improve the above unfairness, this paper presents ABR DELAY mechanism, in which three reference parameters for cell delay are defined, and reflect on the messages of RM(Resource Management) cells. To evaluate our mechanism, we compare the fairness among TCP connections between ABR DELAY mechanism and ABR RRM mechanism. And also we execute simulations on a simple ATM network model where six TCP connections and a background traffic with different RTTs share the bandwidth of a bottleneck link. The simulation results, based on TCP goodput and efficiency, clearly show that ABR DELAY mechanism improves the fairness among TCP connections.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.4
• /
• pp.629-637
• /
• 2006

Currently the research on input-queued ATM switches is one of the most active research fields. Many achievements have been made in the research on scheduling algorithms for input-queued ATM switches and also applied in commerce. The scheduling algorithms have the characteristics of improving throughput, satisfying QoS requirements and providing service fairly. In this paper, we studied on an implementation of scheduler which arbirates the input-queued ATM switches efficiently and swiftly. The proposed scheduler approximately provides 100% throughput for scheduling. The proposed algorithm completes the arbitration for N-port VOQ switch with 4-iterative matching. Also the proposed algorithm has a merit for implementing the scheduling algorithm with 1/2 area compared to that of iSLIP scheduling algorithm which is widely used. The performance of the proposed scheduling algorithm is superior to that of iSLIP in 4-iterative matching. The proposed scheduling algorithm was implemented in FPGA and verified on board-level.

• Journal of the Korea Computer Industry Society
• /
• v.3 no.1
• /
• pp.85-94
• /
• 2002

EMRCA(Explicit Max_min Rate Control Algorithm) switch, which has been proposed in the ATM(Asychronous Transfer Mode) standard, controls the ABR(Available Bit Rate) service traffic in the ATM networks. The ABR service class of ATM networks uses a feedback control mechanism to adapt to varying link capacities. The VS/VD(Virtual Source/Virtual Destination) technique offers the possibility to segment the otherwise end-to-end ABR control loop into separate loops. The improved feedback delay and the control of ABR traffic inside closed segments provide a better performance and QoS(Quality of Service) for ABR connections with respect to throughput, delay, and jitter. This paper is study of an ABR VS/VD flow control method. Linear control theory offers the means to derive correct choices of parameters and to assess performance issues, like stability of the system, during the design phase. The performance goals are a high link utilization, fair bandwidth distribution and robust operation in various environments, which are verified by discrete event simulations. The major contribution of this work is the use of linear control theory to model and design an ABR flow control method tailored for the special layout of a VS/VD switch, the simulation shows that this techniques better than conventional method.

• Journal of IKEEE
• /
• v.1 no.1 s.1
• /
• pp.176-184
• /
• 1997

The Asynchronous Transfer Mode(ATM) networks are being adopted as backbones over various parts of Internet. Also, TCP is one of the most widespread transport protocols, nowdays. It can be used with ATM. But, TCP shows poor end-to-end performance on ATM networks. Effective throughput of TCP over ATM can be quite low when cells are dropped at the congested ATM switch. The low throughput is due to wasted bandwidth as congested link transmits cells from corrupted packets. This paper examines the behavior of TCP over ATM with limited bandwidth in a broadband environment. As multiple VBR sources occupies most of the available bandwidth, there has been a starvation effect, so TCP sources couldn't get the chance of transmitting data. Also, throughput is proportional to the amount of buffer.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.3
• /
• pp.923-934
• /
• 2000