• Journal of the Korea Academia-Industrial cooperation Society
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• v.3 no.4
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• pp.274-279
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• 2002

ATM packet switching technologies for the purpose of the B-ISDN service are focused on high performance which represents good qualities on throughput, packet loss, and packet delay. ATM switch designs on a class of parallel interconnection network have been researched. But these are based on the self-routing function of it. It leads to conflict with each other, and to lose the packets. Therefore, this paper proposes the method based on Sort-Banyan network should be adopted for optimal routing algorithm. It is difficult to expect good hardware complexity. For good performance, a switch design based on the development of new routing algorithm is required. For the design of switch network, the packet distributor and multiplane are proposed. They prevent each packet from blocking as being transmitted selectively by two step distributed decision algorithm. This switch will be proved to be a good performance switch network that internal blocking caused from self-routing function is removed. Also, it is expected to minimize the packet loss and decrease the packet delay according to packet transmission.

• The Transactions of the Korea Information Processing Society
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• v.7 no.6
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• pp.1949-1955
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• 2000

This paper proposes a multistage interconnection ATM switching network without internal blocking. The first is recirculating shuffle-exchange network improved on hardware complexity. The next is connected to Rank network with tree structure. In this network, after the packets transferred to the same output ports are given each priority, only a packet with highest priority is sent to the next, an the others are recirculated to the first. Rearrangeability through decomposition and composition algorithm is applied for the transferred packets in hanyan network and all they arrive at a final destinations. To analyze throughput, waiting time and packet loss ratio according tothe size of buffer, the probabilities are modeled by a binomial distribution of packet arrival.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.9A
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• pp.1535-1541
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• 2001

TCP is the most widely-used transport layer protocol in current Internet, while ATM technology is used to increase the data communication speed at data link layer and network layer. In the TCP-over-ATM architecture, the most significant problems are (i) the partial packet discarding problem, and (ii) the TCP window timeout problem. Several approaches have been proposed to solve the partial packet discard problem and the timeout problem individually, but none of them considered the two problems together. In this paper, we propose an enhanced UBR+ scheme which supports fairness among the TCP connections using UBR+ scheme, and provides protection of damaged VC from the multiple packet losses in the same TCP sliding window. To analyze its performance, we simulate the proposed scheme using OPNET. The simulation results show that the proposed scheme supports fairness, and also increases the throughput by reducing the probability of multiple cell losses in the same TCP window.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.131-134
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• 1998

This paper is describing an ADSL access network configuration by packet mode and analyzed the performance of this ADSL network. We are interesting in difference between ATM mode and packet mode concerning to the performance and service availability. So, this paper has described the characteristics of packet mode ADSL network.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.55-58
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• 1998

In this paper, we describe the design of the ATM adapter circuit in the BSC for IMT-2000 Network. This ATM adapter circuit can convert received ATM cell into TDM data in the BSC and vice versa. In the ATM adapter, we implemented both AAL1 and AAL5 functions to provide constant bit rate voice data and variable bit rate packet data servives, simultaneously.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3B
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• pp.191-199
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• 2003

In this paper, a channel access control algorithm and a dynamic slot allocation algorithm are proposed for rt_VBR services and ABR services in the wireless ATM networks. In the proposed algorithm, rt_VBR terminals that require real-time services transmit a reservation request packet by a RAS minislot. An rt_VBR terminal, which transmitted the reservation request packet, transmits the dynamic parameters by DPS minislot without contention. On the other hand, ABR terminals that have a non-real-time traffic burst transfer a reservation request packet with contention basis. Based on the received dynamic parameters, the base station scheduler allocates uplink data slots as well as DPS minislot into rt_VBR terminals.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.1
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• pp.1-8
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• 1997

A wide class of networking application services, such as video teleconferencing, VOD, LAN bridging, and distributed data processing require multipoint communications. The essential component inteh network to achieve this is a multicast packet switch which is capable of packet replication and switching. In this paper, we propose an efficient mukticast addressing scheme using the smallest number of routing bits which is deterministic lower bound. The new scheme performs all point-to-multipoint connection in radix-2 tree ATM switch like banyan network. Also, we provide a simple radix-2 switch block diagram for achieving our algorithm. And we investigate several addressing schemes for implementing multicasting in radix-r tree ATM switch and evaluate several performance factors, such as complexity of the additional header bits, requirement of the internal speedup and complexity of the major hardware.

• The KIPS Transactions:PartC
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• v.8C no.1
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• pp.88-96
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• 2001

Future mobile communication networks, which consist of ATM-based B-ISDN backbone networks and wireless ATM networks, will provide u user with broadband connection and QoS service. These network systems need the lossless handoff methods which support user mobility, satisfy ATM features such as ATM cell ordering and no ATM cell duplication and minimize buffer requirement for ATM cell buffering. In this paper we suggest a multicast-based handoff method to supp$\alpha$t lossless connection as well as to minimize buffer overhead. It establishes a dynamic multicast connection between source terminal and wireless member AP (access point)s. When the mobile terminal receives data packet correctly, it notifies the positive acknowledgement of the packet to all member APs. And member APs then release the MT related temporary buffer space for MT's future movement. Therefore member APs can eliminate unnecessary buffer usage and manage the buffer space efficiently. Analysis result shows that our handoff method has better performance in buffer requirement for lossless and seamless connection services over VCT (virtual connection tree) method and other dynamic multicast-based handoff methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4C
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• pp.308-315
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• 2002

Guaranteed frame rate (GFR) service has been defied to provide minimum cell rate (MCR) guarantees for virtual connections (VCs) carrying Internet traffic in ATM networks and allow them to fairly share residual bandwidth. The simplest switch implementation mechanism to support the GFR service in ATM networks consists of the frame-based generic cell rate algorithm (F-GCRA) frame classifier and the early packet discard (EPD)-like buffer acceptance algorithm in a single FIFO buffer. This mechanism is simple, but has foiled to guarantee the same bandwidth as an MCR to a VC that has reserved a relatively large MCR. This paper applies the packet spacing scheme to TCP traffic to alleviate its burstness, so as to guarantee a larger MCR to a VC. In addition, the random early detection (RED) scheme is added to the buffer acceptance algorithm in order to improve fairness in use of residual bandwidth. Simulation results show that the applied two schemes improve a quality of service (QoS) in the GFR service for the TCP traffic.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.