• Journal of the Korea Society of Computer and Information
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• v.7 no.3
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• pp.80-91
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• 2002

A general goal of the AT%(Asynchronous Transfer Mode) network is to support connect across various network. On ATM networks, ABR services are provided using the remained ban after allocation CBR and VBR traffic. Realtime services such as transmitting audio or video data may be provided using CBR ado VBR which have a constrained transmission delay, but in these cases, the communications bandwidth may be wasted. In this paper a simulation has been performed to compare and evaluate the performance between the ERICA(Explicit Rate Indicate Avoidance) and EPRCA(Enhanced Proportional Rate Control Algorithm) switches which use Explicit Rate switch algorithm for ABR switch. The variation of the ACR at the source end system, the queue length, the utilization rate of the link bandwidth and the share fairness at the transient and steady states are used as the evaluation criteria for the simulation. As a result of simulation, ERICA algorithm switch was ten times long compared to ERPCA switch to achieve assigned fair share. so EPRCA switch is superior to ERICA about load response. For Fair share and stability, ERICA switch is excellent to EPRCA switch.

• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.74-81
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• 2001

In this paper. the architecture of a high-speed ATM router using ATM switch is studied and the performance of the high-speed ATM router is analyzed through simulation. The high-speed ATM router using ATM switch is able to reduce the load of router and the processing time of a packet in the router. The size of router buffers has been studied through simulation processes for the analysis of performance capacity in due course of making changes in routing time(RT), which is the performance capacity parameters of high-speed ATM routers, flow table size(FS), flow live time(FT) and input circuit efficiencies. The result of this study can be used as the source material for analyzing the suitability of equipment in upgrading networks and applying high-speed ATM routers by using ATM switches.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.265-268
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• 1998

This paper evaluates the VSN(Virtual switch Network) characteristics in the internal call processing of IMT-2000 switching system, which is composed of VSN instead of ATM switch network. In results, internal call establishment delay is increased approximately 5.4msec than the conventional ATM switching system. The evaluated condition is the load 0.8, and the 100km distance between VSNs. It is confirmed that the VSN has the potentiality in the practical implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.390-393
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• 2003

In this paper, we study on an implementation of cell scheduler which arbitrates the ATM exchange efficiently and swiftly. The designed ATM cell scheduler of this paper is based on iSLIP scheduling algorithm. It is aimed at the high-speed implementation. The implemented cell scheduler approximately provides 100% throughput for cell scheduling. We present a basic structure for cell scheduler and describe by using the HDL and perform behavior level and timing simulation. The cell scheduler of this paper is designed to support 8-port switch fabric and can expand in 32-port switch fabric. The cell scheduler for supporting the 8-port switch fabric is designed in 2-stage pipelines for the grant and accept stages respectively.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.11
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• pp.25-33
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• 1997

The end-to-end rate-based control mechanism is used for the flow control of the ABR service to allow much more flexibility in ATM switching system. To accommodate the ABR service effciently many algorithms such as EFCI, EPRCA, ERICA, and CAPC2 have been proposed for the switch algorithm. ABR cells and related RM cells are received at the ATM switch fabric transparently without any processing. And then cells received from the traffic source are queued in the ABR buffer of switching system. The ABR buffer usually has some thresholds for easy congestion control signal transmission. Whatever we use, therefore, these can be many ABR traffic control algorithms to implement the ABR transfer capability. The genertion of congestion indicate signal for ABR control algorithms is determined by ABR buffer satus. And ABR buffer status is determined by ABR cells transfer ratio in ATM switch fabrics. In this paper, we presented the functional structures for control of the ABR traffic capability, proposed the readout scheduling, cell slot allocation of output link and the buffer allocation model for effective ABR traffic guranteeing with considering CBR/VBR traffics in ATM switch. Since the proposed readout scheduling scheme can provide more avaliable space to ABR buffer than existing readout scheduling scheme, generation rate of a SEND signal, that is, BCN signal in destination node can be increased for ABR call connection. Therefore, the proposed scheme, in this paper, can be appropriate as algorithm for effective ABR traffic service on output link of ATM switching node.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.56-63
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• 2000

In this paper, we design new high performance ATM switch architectures based on a Generalized Shuffle network(GSN). The GSN is a distributed network topology with the number of nodes in O(N). To improve the throughput of the switch, a layering strategy called Weaved GSN(WGSN). WGSN has an additional connection links between switching elements which locate in the same position of adjacent GSNs. The analysis and simulation are performed under uniform and full load conditions, and the results show that the proposed switch has better throughput and cell loss performance when compared with other banyan-based switch architectures known so far.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.115-123
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• 2002

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter. The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms. The Proposed switch acquires control over priority transmission through the REQ signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the Proposed switch under uniform traffic conditions.

• Journal of the Korea Society of Computer and Information
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• v.11 no.1 s.39
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• pp.157-165
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• 2006

This paper proposes a new output-buffered multicast ATM switch with tandem crosspoints switching fabric, named the MTCOS(Multicast Tandem Crosspoint Output-buffered Switch). The MTCOS consists of multiple simple crosspoint switch fabrics, named TCSF(Tandem Crosspoint Switch Fabric) , and concentrated output buffers for efficient multicasting. The TCSF resolves the cell delay deviation problem which the self-routing crossbar switches inherently have. Further, it offers multiple concurrent pathes from one input to multiple output ports. It also provides multi-channel switching by easy software configuration and has several desirable characteristics such as scalability, high Performance, and modularity. A shared traffic concentration and output queuing strategies of the MTCOS results in lower cell loss as well as lower cell delay time over a wide range of multicast traffic. Furthermore, it has lower hardware complexity than that of the SCOQ and Knockout multicast switch to achieve the same Knockout concentration rate as the conventional switches. It is shown that the proposed switch can be easily applied to design high performance for any multicast traffic by analytic analysis and computer simulation.

• Journal of the Korea Society of Computer and Information
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• v.8 no.2
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• pp.97-105
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• 2003

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The Proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output Port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms . The proposed switch acquires control over priority transmission through the REd signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the proposed switch under non-uniform random traffic conditions.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.10
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• pp.8-16
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• 1992

Despite recent advances in electrical switch architectures, the practical switch performance is limited by both the technological and physical constraints of electrical device and wiring. Though an optical switch can have good features, optical devices are of poor quality. Therefore, we propose and study the switching architecture based on free-space optical interconnections and electrical logic devices. And an exchanging method using packets with a parallel form is introduced to solves the blocking problem of the switch that resulted from switching packets with a serial form. The free-space optical interconnections overcome the defects of electrical switch, such as, the complex connections of the wires. The proposed and demonstrated switch is nonblocking, simple and high performable. Other attractive features of the proposed switch include the guarantee of first-in first-out packet sequence. In this thesis, we also discuss the performance of proposed switch and show the experimental results of the 4$\times$4 switch.