• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.12
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• pp.584-589
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• 2001

This paper presents an implementation method of multi-channel synchronized phasor measurement device, which is based on the ASIC implementation of the sliding-DFT. A time-shared multiplier structure is proposed to minimize the number of gates required for the implementation. The design is verified by the timing simulation of its operation. The effect of coefficient approximation in the recursive implementation of the sliding-DFT is analytically derived and verified with the computer simulations.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.109-112
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• 2000

The satellite communications are expected to play an important role to provide broadband multimedia services in the 21st century. According to this requirements, this paper describes the design and implementation of ATM-based high speed satellite modem ASIC chipset. The ASIC chip consists of three main parts, CODEC, Modulator and Demodulator. It supports burst and continuous mode operation with TDMA frame consisted of Reference bursts, Inbound burst, and Traffic burst. The maximum transmission rate is OC-3 (155Mbps) and the maximum operating clock speed is 220MHz. This ASIC chip was implemented with 0.25um CMOS technology.

• Journal of the Korean Society of Industry Convergence
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• v.2 no.2
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• pp.103-108
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• 1999

The paper describes a implementation of space vector pulse-width modulation voltage source inverter and interfacing of DSP using field programmable gate array(FPGA) for a induction motor vector control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QLl6X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed Application Specific Integrated Circuit(ASIC) for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance induction motor drives with a voltage source inverter. Simulation and implementation results are shown to verify the usefulness of ASIC in a motor drive system and power electronics applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.1-8
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• 2018

Recently, the convolutional neural network shows high performance in many computer vision tasks. However, convolutional neural networks require enormous amount of operation, so it is difficult to adopt them in the embedded environments. To solve this problem, many studies are performed on the ASIC or FPGA implementation, where an efficient representation method is required. The fixed-point representation is adequate for the ASIC or FPGA implementation but causes a performance degradation. This paper proposes a separate optimization of representations for the convolutional layers and the batch normalization layers. With the proposed method, the required bit width for the convolutional layers is reduced from 16 bits to 10 bits for the ResNet-50 neural network. Since the computation amount of the convolutional layers occupies the most of the entire computation, the bit width reduction in the convolutional layers enables the efficient implementation of the convolutional neural networks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.7B
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• pp.1006-1012
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• 2001

본 논문에서는 다른 클럭원들을 갖는 서로 다른 오실레이터에 의해 발생된 비동기 클럭을 입력으로 받아 동기신호로 변환시키는 기능과 그 중 어느 한 클럭이 동작하지 않더라도 동작하는 클럭을 계속 유지하여 클럭 중단의 위험을 제거한 안전모드를 추가한 기능의 구현을 기술한다. 특히, 통신 분야에서 ASIC으로 Chip을 개발할 때 다중 클럭의 사용은 필연적이며 비동기 신호를 동기신호로 변환하는 기능의 구현은 기본적이면서도 중요한 부분이다. 이 회로는 VHDL로 구현이 되었으며 다중 클럭 관련 ASIC 구현에 기본적으로 응용이 가능하다.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2758-2760
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• 1999

ASIC chip design for motor control has been a subject of increasing interest since effective system-on-a-chip design methodology was developed. This paper investigates the design and implementation of ASIC chip for speed control of induction motor using VHDL which is a standarded hardware description language. The presented system is implemented using a simple electronic circuit based on FPGA.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.82-85
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• 1998

Because ATM was originally designed for the optical fiber environment with bit error rate(BER) of 10-11, it is difficult to maintain ATM cell extraction capability in wireless environment where BER ranges from 10-6 to 10-3. Therefore, it must be proposed the algorithm of ATM cell extraction in wereless environment. In this paper, the frame structure and synchronization algorithm satisfyling the above condition are explained, and the new ASIC implementation method of this algorithm is proposed. The known method using shift register needs so many gates that it is not suitable for ASIC implementation. But in the proposed method, a considerable reduction in gate count can be achieved by using random access memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.980-986
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• 2002

In the fast data communication system, synchronized by a clock source, the loss of data will often occur due to several reasons as a differential routing path between data and clock, a differential propagation delay of components or an unstable phase of clock and data by external noise. In this paper, we describe the ASIC implementation of the data compensation circuit which can detect the data loss from above problems and recovery to original data with stable synchronization. Especially it supports a strong stability and a good BER in the communication system for fast data transfer as optic area. This circuit is implemented by Verilog HDL and available to the digital ASIC implementations related to fast data transfer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.1885-1896
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• 1996

This paper describes the implementation of the AVT(Automatic video Tracker) using ASIC. The basic tracking algorithm is based on the spatio-temporal gradient method, and adaptive window sizing, track state decision algorithm were also realized. Newly developed ASIC performs recursive image filtering, extraction of spatio-temporal gradient/gradient functions of image in field rate. Using the FPGA/ASIC, the tracker was simply realized in one board type which can be easily applied to various image system. We conformed ASIC operation by computer simulation and tested the system in real tracking situations. From the result, the system can track the moving target which has a velocity of 2-3 pixel/field and a size of varying from 2 to 128 pixes. Also fast refresh rateof motion estimation(60Hz) improves the characteristics of servoing system which forms feedback loop with the tracker.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.439-442
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• 2002

전력선을 이용하여 신뢰성 높은 데이터 통신을 하기 위해서는 다양한 변복조 방법 및 채널코딩의 적용이 필요하다. 본 논문에서는 이러한 변복조 및 채널코딩중에서 FSK 변복조와 HDLC코딩 방식을 적용하여 데이터 통신 시 발생하는 신호감쇠와 잡음을 제거하고, 신뢰성 있는 데이터 전송환경을 구축하기 위해 전력선 통신용 모뎀을 CPLD를 바탕으로 한 ASIC으로 구현하고 실제환경에 적용하였다.