• Title/Summary/Keyword: ARMTTDMI

Search Result 5, Processing Time 0.024 seconds

Embedded Operating System using the Single Address Space(SAS) Architecture (Single Address Space(SAS) Architecture를 이용한 Embedded Operating System)

  • An, Gwang-Hyeok
    • Proceedings of the KIEE Conference
    • /
    • 2003.11c
    • /
    • pp.608-611
    • /
    • 2003
  • A large part of the embedded system, compared with the PC, have low performance CPU and small memory. So the embedded operating system fits the condition of that hardware system. A Single Address Space (SAS) OS has the operating system and all applications in the single address space. The SAS architecture enhances sharing and co-operation, because addresses have a unique interpretation. Thus, pointer-based date structures can be directly communicated and shared between programs at any time, and can be stored directly on storage. The key point of the SAS OS on the embedded system is the low overhead inter-action between programs in process and usage. So SAS OS can be ported on the low performance CPU. In this paper, we design the SAS OS (named emNOS, Embedded Network Operating System) on the ARMTTDMI processor. Finally we show the benefits of the SAS OS on the embedded system.

  • PDF

Design of 32 bits tow Power Smart Card IC (32 비트 저전력 스마트카드 IC 설계)

  • 김승철;김원종;조한진;정교일
    • Proceedings of the IEEK Conference
    • /
    • 2002.06b
    • /
    • pp.349-352
    • /
    • 2002
  • In this Paper, we introduced 32 bit SOC implementation for multi-application Smart Card and described the methodology for reducing power consumption. It consists of ARMTTDMI micro-processor, 192 KBytes EEPROM, 16 KB SRAM, crypto processors and card reader interface based on AMBA bus system. We used Synopsys Power Compiler to estimate and optimize power consumption. Experimental results show that we can reduce Power consumption up to 62 % without increasing the chip area.

  • PDF

32 Bit RISC Core modeling using SystemC

  • 최홍미;박성모
    • Proceedings of the IEEK Conference
    • /
    • 2002.06b
    • /
    • pp.325-328
    • /
    • 2002
  • In this paper, we present a SystemC model of a 32-Bit RISC core wi)ich is based on the ARMTTDMI architecture. The RISC core model was first modeled in C for architecture verification and then refined down to a level that allows concurrent behavior lot hardware timing using the SystcmC class library. It was driven in timed functional level that uses handshake protocol. It was compiled using standard C++ compiler. The functional simulation result was verified by comparing the contents of memory, the result of execution with the result from the ARMulator of ADS(Arm Developer Suite).

  • PDF

Design of Fast Parallel Floating-Point Multiplier using Partial Product Re-arrangement Technique (효율적인 부분곱의 재배치를 통한 고속 병렬 Floating-Point 고속연산기의 설계)

  • 김동순;김도경;이성철;김진태;최종찬
    • Proceedings of the IEEK Conference
    • /
    • 2001.06e
    • /
    • pp.47-50
    • /
    • 2001
  • Nowadays ARM7 core is used in many fields such as PDA systems because of the low power and low cost. It is a general-purpose processor, designed for both efficient digital signal processing and controller operations. But the advent of the wireless communication creates a need for high computational performance for signal processing. And then This paper has been designed a floating-point multiplier compatible to IEEE-754 single precision format for ARMTTDMI performance improvement.

  • PDF

Implementation of the contact and contactless IC Card OS for Java Card (자바 카드에서 접촉 및 비접촉 겸용 IC카드 OS의 설계 및 구현)

  • 주홍일;손수호;전용성;전성익
    • Proceedings of the IEEK Conference
    • /
    • 2002.06a
    • /
    • pp.375-378
    • /
    • 2002
  • This paper describes tile design and implementation of contact and contactless If card OS(Operating System) for Java Card, namely JCOS(Java Card 05). The JCOS complies with ISO/IEC 7816 and IS0/1EC 14443 standards. The JCOS conforms to Java Card 2.1.2 specifications. The JCOS is running on 32-bit ARMTTDMI with public key crypto-coprocssor. This paper describes only the dual-interface protocol of the JCOS which supports contact and contactless applications in a single chip. The JCOS has been completed with our sample banking service and access control service in ETRI up to now.

  • PDF