• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.261-267
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• 2002

In SOC(System On a Chip) designs, reducing time and cast for design verification is the most critical to improve the design productivity. this is mainly because the designs require co-verifying HW together with SW, which results in the increase of verification complexity drastically. In this paper, to cope with the verification crisis in SOC designs, we propose a new verification methodology, so called integrated co-verification, which lightly combine both co-simulation and co-emulation in unified and seamless way. We have applied our integrated co-verification to ARM/AMBA platform-based co-verification environment with a commercial co-verification tool, Seamless CVE, and a physical prototyping board. The experiments has shown clear advantage of the proposed technique over conventional ones.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.670-673
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• 2008

Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP verified doubly in view of hardware structure together with algorithmic verification, was implemented on the Altera Excalibur FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.126-133
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• 2006

This paper describes an AMBA-based IP to perform forward and inverse transform and quantization required in the H.264 video compression standard. The transform and quantization circuit was optimized for area and performance. The AHB wrapper was added to the circuit for the AMBA-based operation. The user of the IP can specify how long the bus may be occupied by the IP and also where the video data are stored in the external memory. The function of the proposed IP based on AMBA Specification was verified on the platform board with Xilinx FPGA and ARM9 processor. We fabricated an MPW chip using $0.25{\mu}m$ standard cells and observed its correct operations on silicon.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.84-89
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• 2007

In order to design and test an SoC modem for high speed communication, the platform with the architecture of such high speed communication is needed. That platform is needed for testing large data in speed of 500Mbps. This paper shows that transmission data can be uploaded and downloaded by 250Mbps between a virtual modem target board and a PC through the AHB-PCI IP and the speed of based on DPRAM and PCI.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.273-278
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• 2012

In this contribution, we design and implement an SPI hardware interface for the microprocessor to communicate with the MMC (Multi-Media Card) in an embedded system. Proposed architecture is compatible with the APB in AMBA bus architecture. Embedding OS in an embedded system means a big burden in terms of hardware and software ending up with performance decline. In this paper, we adopt the concept of SPI communication without using OS in the embedded system and implement in a form of FPGA chip. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency, which satisfied our target speed.

• Proceedings of the Korea Contents Association Conference
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• 2005.05a
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• pp.443-447
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• 2005

EMAST(Embedded Mobile Automatic System for Telematics) is implemented in SoC using the CAN and ARM Processor. For the general usage, EMAST must satisfy the two condition. First, Mobile internal interface is to be designed to support Differential Transceiver, Optical Transceiver and Wireless Transceiver Second, it should be supporting the interface between terminals using EMAST and telematics networks. In this paper, we propose EMAST structure and the efficient interface structure between EMAST and each mobile units.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.459-462
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• 2008

By using RFID technology in order to manage public traffic management, RFID system and middleware software with PXA255 ARM chip is developed and is capable of operating the traffic card. The developed RFID system consists of 13.56MHz RFID R/W, wireless LAN (IEEE802.11.a/b), Wibro (IEEE802.16), TFT-LCD to display information, and embedded system to collect a charge information, etc. By applying developed system, basic infra-structure capable of supporting various service of u-Traffic can be effectively applied.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.2
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• pp.148-154
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• 2009

In this paper, an embedded Kalman filter for a time-delayed controller is designed on an FPGA to estimate accelerations of the robot arm. When the time-delayed controller is used as a controller, the inertia estimation along with accelerations is needed to form the control law. Although the time-delayed controller is known to be robust to cancel out uncertainties in the nonlinear systems, performances are very much dependent upon estimating the acceleration term ${\ddot{q}}(t-{\lambda})$ along with inertia estimation ${\hat{D}}(t-{\lambda})$. Estimating accelerations using the finite difference method is quite simple, but the accuracy of estimation is poor specially when the robot moves slowly. To estimate accelerations more accurately, various filters such as the least square fit filter and the Kalman filter are introduced and implemented on an FPGA chip. Experimental studies of following the desired trajectory are conducted to show the performance of the controller. Performances of different filters are investigated experimentally and compared.

• Journal of IKEEE
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• v.21 no.1
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• pp.92-95
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• 2017

In this paper, we proposed a way to improve function of small scale GP-GPU. Instead of using superscalar which increase scheduling-complexity, we suggested the application of simple core to maximize GP-GPU performance. Our studies also demonstrated that simplified Stream Processor is one of the way to achieve functional improvement in GP-GPU. In addition, we found that developing of optimal thread-assigning method in Warp Scheduler for specific application improves functional performance of GP-GPU. For examination of GP-GPU functional performance, we suggested the thread-assigning way which coordinated with Deep-Learning system; a part of Neural Network. As a result, we found that functional index in algorithm of Neural Network was increased to 90%, 98% compared with Intel CPU and ARM cortex-A15 4 core respectively.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2646-2648
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• 2001

In this paper, the development of Power Line Communication(PLC) device for white goods is presented. The commercial PLC chip-set is used for the modem device of white goods. As a PLC device for white goods, an ARM720 u-controller and a windows CE 3.0 are adopted. UPnP (Universal Plug and Play) that is applied for home network middle ware in implemented system. In addition, application programming and emulator for home appliance are implemented using UPnP standard ver 1.0.