• Journal of the Korea Society of Computer and Information
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• v.17 no.11
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• pp.1-10
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• 2012

In this paper, the extension of the addressing mode in the 16-bit Thumb instruction set architecture is proposed to improve the performance of 16-bit Thumb code. The key idea of the proposed approach is the introduction of new addressing modes for more frequent instructions by using the saved bits from the reduction of the register fields in less frequently used instructions. The proposed approach adopts efficient addressing modes from the 32-bit ARM architecture, which is the superset of the 16-bit Thumb architecture. To speed up access to a data list, scaled register offset addressing mode and post-indexed addressing mode are introduced for load and store instructions. Experiments show that the proposed approach improves performance by an average of 8.5% when compared to the conventional approach.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1992.04a
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• pp.127-132
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• 1992

To relize the future intelligent robot the development of a special-purpose processor for a coordinate transformation is evidently challenging task. In this case the complexity of a hardware architecture strongly depends on the adopted algorithm. In this paper we have used an inverse kinemetics algorithm based on incremental unit computation method. This method considers the 3-axis articulated robot as the combination of two types of a 2-axis robot: polar robot and 2-axis planar articulated one. For each robot incremental units in the joint and Cartesian spaces are defined. With this approach the calculation of the inverse Jacobian matrix can be realized through a simple combinational logic gate. Futhermore, the incremental computation of the DDA integrator can be used to solve the direct kinematics. We have also designed a hardware architecture to implement the proposed algorithm. The architecture consists of serveral simple unitsl. The operative unit comprises several basic operators and simple data path with a small bit-length. The hardware architecture is realized byusing the EPLD. For the straight-line motion of the KAIST arm we have obtained maximum end effector's speed of 12.6 m/sec by adopting system clock of 8 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.123-130
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• 2004

This paper describes a multiplier architecture optimized for 32 bit RISC processor with 3-stage pipeline. The multiplier of ARM7, the target processor, is variably carried out on the execution stage of pipeline within 7 cycles. The included multiplier employs a modified Booth's algerian to produce 64 bit multiplication and addition product and it has 6 separate instructions. We analyzed several multiplication algorithm such as radix4-32${\times}$8, radix4-32${\times}$16 and radix8-32${\times}$32 to decide which multiplication architecture is most fit for a typical architecture of ARM7. VLSI area, cycle delay time and execution cycle number is the index of an efficient design and the final multiplier was designed on these indexes. To verify the operation of embedded multiplier, it was simulated with various audio algorithms.

• KIISE Transactions on Computing Practices
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• v.21 no.12
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• pp.745-750
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• 2015

LiDAR(Light Detection and Ranging) technology provides realistic 3-dimension image information, and it has been widely utilized in various fields. However, the utilization of this technology in the military domain requires prompt responses to dynamically changing tactical environment and is therefore limited since LiDAR technology requires complex processing in order for extensive amounts of LiDAR data to be utilized. In this paper, we introduce an Unmanned Aircraft Platform Based Real-time LiDAR Data Processing Architecture that can provide real-time detection information by parallel processing and off-loading between the UAV processing and high-performance data processing areas. We also conducted experiments to verify the feasibility of our proposed architecture. Processing with ARM cluster similar to the UAV platform processing area results in similar or better performance when compared to the current method. We determined that our proposed architecture can be utilized in the military domain for tactical and combat purposes such as unmanned monitoring system.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.286-288
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• 2003

본 논문에서는 서로 다른 네트워크간의 다양한 프로토콜과 이종의 트래픽을 동시에 처리할 수 있는 네트워크용 SoC (System-on-a-Chip) 프로세서를 구현하였다. 제작된 네트워크 SoC 프로세서는 ARM 프로세서 코어와 ATM(Asynchronous Transfer Mode) 블록, 10/100 Mbps 이더넷 볼록, 스케쥴러, UART 등을 이용하였고 각 블록은 AM8A (Advanced Microcontroller Bus Architecture) 버스로 연결하였다. SoC 프로세서는 CADENCE사의 VerilogHDL을 이용하여 설계하였고 0.35$\mu\textrm{m}$ 셀 라이브러리를 이용하여 검증하였다. 구현된 칩은 총 게이트수가 312,000개이며 칠의 최대 동작 주파수는 50MHz 이다.

• Journal of Mechanical Science and Technology
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• v.19 no.6
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• pp.1253-1267
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• 2005

Misalignment can be an important problem in the integration of GPS/INS. Observability analysis of the alignment errors in the integration of low-grade inertial sensors and multi-antenna GPS is presented in this paper. A control-theoretic approach is adopted to study the observability of time-varying error dynamics models. The relationship between vehicle motions and the observability of the errors in the lever arm and relative attitude between GPS antenna array and IMU is given. It is shown that alignment errors can be made observable through maneuvering. The change of acceleration makes the components of the relative attitude error that are orthogonal to the direction of the acceleration change observable. The change of angular velocity makes the components of the lever arm error that are orthogonal to the direction of the angular velocity observable. The motion of constant angular velocity has no influence on the estimation of the lever arm.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.3
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• pp.145-153
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• 2013

Virtualization technology has been applied in IA-32 based server or desktop systems. Recently it has been applied in ARM based mobile systems. Virtualization technology provides many useful features that are not possible in operating system level such as isolation, interposition, encapsulation and portability. In this research, we implement an ARM based VMM(Virtual Machine Monitor) by using the following techniques. First, we use "emulation" to virtualize the processor. Second, we use "shadow page tables" to virtualize the memory. Finally, we use a simple "pass-through I/O" to virtualize the device. Currently the VMM runs ARM Linux kernel 3.4.4 on a BeagleBoard-xM, and we evaluated the performance of the VMM using lmbench and dhrystone. The result of the evaluation shows that our VMM is slower than Xen on ARM that is implemented using paravirtualization but has good performance among the VMMs using full-virtualization.

• Journal of the Korea Society of Computer and Information
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• v.17 no.2
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• pp.1-11
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• 2012

Recently, we have seen several implementations that virtualize the ARM architecture. Since the current ARM architecture is not possible to be virtualized using the traditional technique called "trap-and-emulation", we usually detect all virtualization sensitive instructions during the run-time of a guest kernel and emulate them virtually rather than executing them directly. The emulation for virtualization is usually implemented either by binary translation or interpretation. Our research is about how to improve the performance of emulation for virtualization based on interpretation. The interpretation usually requires a few steps: instruction fetching, instruction decoding and instruction executing. In this paper, we propose a method that decodes all virtualization sensitive instructions during the compilation time of a guest kernel and reduces the time required for interpretation during the run time of the guest kernel. Our method provides both implementation simplicity and performance improvement of emulation for virtualization based on interpretation.

• Physical Therapy Korea
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• v.23 no.2
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• pp.84-92
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• 2016

Background: Strengthening the supraspinatus is an important aspect of a rehabilitation program for subacromial impingement and tendinopathy. Many authors recommended empty-can (EC), full-can (FC), and prone full-can (PFC) exercises to strengthen the supraspinatus. However, no ultrasonography study has yet investigated supraspinatus muscle architecture (muscle thickness; MT, pennation angle; PA, fiber bundle length; FBL) in relation to supraspinatus strengthening exercises. Objects: The purpose of this study was to compare the architecture (MT, PA, and FBL) of the supraspinatus muscle during three different types of exercises (EC, FC, and PFC) using diagnostic ultrasound. Methods: Participants performed three different exercises: (A) EC; the arm was maintained at $60^{\circ}$ abduction with full internal rotation in the sitting position, (B) FC; the arm was maintained at $60^{\circ}$ abduction with full external rotation in the sitting position, and (C) PFC; the arm was maintained at $60^{\circ}$ abduction with full external rotation in the prone position. Ultrasonography was used to measure the MT, PA and FBL of the supraspinatus. One-way repeated analysis of variance with Bonferroni's post-hoc test was used to compare between the three exercises and the initial position of each exercise. Results: Compared with each initial position, the FC exercise showed the greatest mean difference in muscle architecture properties and the PFC exercise showed the least mean difference. Conclusion: The findings suggest that the FC exercise position may have an advantage in increasing the amount of contractile tissue or producing muscle power and the PFC exercise position may be useful in a rehabilitation program because it offers the advantage of maintaining the muscle architecture properties.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.5
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• pp.1022-1029
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• 2009

What Ubiquitous means "being or existing anywhere, anytime"in Latin, which is, in other words, the users are able to access the network no matter where they are, what kind of network or computer terminals they use. This paper focuses on the implementation of hardware system. The first part of the sytem is the sensor node which transmits the sensor data from node to ARM11 platform through the Zigbee network wirelessly. The other part of the system is the ARM11 platform which receives and displays the sensor data. ARM11 platform is sink node. The ARM11 platform is based on ARM11 architecture and ported with Linux OS. Qtopia is used as Window Manager in order to make applications. The highly efficient ARM11 processor, S3C6400 MPC is the main part of the ARM11 platform.