• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.146-151
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• 2021

We introduce an arbitrary waveform generation method and its H/W implementation case based on Rademacher and Walsh function. According to the orthogonal and periodic features of Rademacher and Walsh function, simple calculations can generate arbitrary waves with affordable logics. We implemented an FPGA-based AWS using above two functions, and verified. HDL simulation shows the proposed idea can draw desired analog test waveforms very fast, and its H/W size is promising to Built-Out Self-Test(BOST) logics for AI ICs.

• Electronics and Telecommunications Trends
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• v.36 no.3
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• pp.1-11
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• 2021

In this study, we analyze the automotive chip ecosystem that recently caused the global supply shortage, and attempt to derive policy implications for us from the conclusion. Automotive chips are critical parts that control various systems so that a vehicle can drive itself or operate with electricity. The current shortage in supply and demand for automotive chips is due to the inconsistency between supply and demand between automotive chip companies and car manufacturers. To promote the automotive chip industry, new investment incentives, tax cuts, and human resource training are needed.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• Electronics and Telecommunications Trends
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• v.39 no.3
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• pp.98-106
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• 2024

Advanced packaging is emerging as a core technology owing to the increasing demand for multifunctional and highly integrated semiconductors to achieve low power and high performance following digital transformation. It may allow to overcome current limitations of semiconductor process miniaturization and enables single packaging of individual devices. The introduction of advanced packaging facilitates the integration of various chips into one device, and it is emerging as a competitive edge in the industry with high added value, possibly replacing traditional packaging that focuses on electrical connections and the protection of semiconductor devices.

• Journal of the Korean Vacuum Society
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• v.4 no.1
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• pp.18-25
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• 1995

건식, 습식, 건식/습식 산화분위기로 성장한 게이트 산화막 위에 AI, 인 도핑된 다결정시리콘, 비정질 실리콘/인 도핑된 다결정 실리콘을 증착하여 제작한 금속-산화물-반도체(metal-oxide-semiconductor:MOS)의 전기적 특성을 순간 절연파괴(TZDB), 정전용량-전압(C-V)과 경시절연파괴(TDDB)로 평가하였다. AI 게이트에서 습식산화막과 건식산화막의 평균 파괴전계는 각각 9.0MV/cm, 7.7MV/cm이였고, 습식산화막의 평균 파괴전계가 8.4MV/cm 이였으며, AI 게이트보다 0.6MV/cm 정도 낮았다. 이것은 다결정 실리콘/습식산화막 계면에서 인(phosphorus) 확산으로 다결정 실리콘의 grain 성장과 산화막의 migration에 의한 roughness 증가에 기인한다. 그러나 다결정 실리콘/건식산화막 계면에서 roughness 증가는 없었다. 다결정 실리콘 게이트에서는 건식/습식 산화막이 건식산화막과 습식산화막보다 평균 파괴전계와 절연파괴전하(QBD)가 높았다. 또한 다결정/비정질 실리콘 게이트에서는 습식산화막의 평균 파괴전계가 8.8MV/cm이였으며, 다결정 실리콘 게이트에서보다 0.4MV/cm 정도 높았다. 다결정/비정질 실리콘 구조는 앞으로 VLSI 적용에 있어서 게이트 전극으로 매우 유용할 것이다.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.11a
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• pp.701-704
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• 2023

본 연구는 반도체 제조 과정에서 생산 가용 능력이 저하되는 시점을 조기 탐지하기 위한 프레임워크를 제안한다. 이를 위해 데이터 패턴의 불규칙한 변동이 잦은 환경에서 모델의 재학습 없이 최적의 성능을 유지할 수 있도록 온라인 학습 방식을 활용하였다. Augmented Dicky-Fuller test 를 통해 데이터의 정상성 여부를 검정하고, 데이터에 변화가 있을 경우 학습 모델은 지속적으로 업데이트된다. 특히, 상한 재공재고는 생산량과 직결되는 주요 지표로써, 낮게 예측된 시점에서 주요 원인 변수를 파악하는 것이 중요하다. 따라서 정확도와 효율성 측면에서 다른 모델 대비 가장 우수한 성능을 보였던 제안 기법에 shapley additive explanations(SHAP)을 적용하여 생산 저하 시 문제가 되는 원인 변수를 분석하고자 하였다.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.108-112
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• 2023

Precision manufacturing technology is rapidly developing due to the extreme miniaturization of semiconductor processes to comply with Moore's Law. Accurate and precise alignment, which is one of the key elements of the semiconductor pre-process and post-process, is very important in the semiconductor process. The center detection of wafer align marks plays a key role in improving yield by reducing defects and research on accurate detection methods for this is necessary. Methods for accurate alignment using traditional image sensors can cause problems due to changes in image brightness and noise. To solve this problem, engineers must go directly into the line and perform maintenance work. This paper emphasizes that the development of AI technology can provide innovative solutions in the semiconductor process as high-resolution image and image processing technology also develops. This study proposes a new wafer center detection method through variable thresholding. And this study introduces a method for detecting the center that is less sensitive to the brightness of LEDs by utilizing a high-performance object detection model such as YOLOv8 without relying on existing algorithms. Through this, we aim to enable precise wafer focus detection using artificial intelligence.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.4
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• pp.127-132
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• 2022

Among the electrical components mounted on railroad cars, the largest load is the main transformer, which has a low power density of 0.2~0.4 MVA/ton due to the low operating frequency(60Hz), which is an important factor for weight reduction. Therefore, research on molded transformers, semiconductor transformers, etc. is being actively conducted at Domestic and foreign in order to improve the main transformer for railway vehicles. Meanwhile, attempts are being made to apply a permanent magnet synchronous motor (PMSM) to replace an induction motor as a traction motor that is mostly applied to domestic and foreign railway vehicles. Permanent magnet synchronous motors (PMSMs) can secure higher power density and efficiency compared to induction motors, but have disadvantages in that the materials required for manufacturing are expensive and design is somewhat difficult compared to induction motors. Considering these problems, in this paper, we suggest that a small and lightweight semiconductor transformer is applied, and a simple structure, high torque, low cost SRM can be applied in accordance with the requirements such as weight reduction and high efficiency of railroad vehicles. content.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.10
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• pp.1403-1408
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• 2021

Recently, FPGA-based AI processors are being studied actively. Deep convolutional neural networks (CNN) are basic computational structures performed by AI processors and require a very large amount of multiplication. Considering that the multiplication coefficients used in CNN inference operation are all constants and that an FPGA is easy to design a multiplier tailored to a specific coefficient, this paper proposes a methodology to optimize the multiplier. The method utilizes 2's complement and distributive law to minimize the number of bits with a value of 1 in a multiplication coefficient, and thereby reduces the number of required stacked adders. As a result of applying this method to the actual example of implementing CNN in FPGA, the logic usage is reduced by up to 30.2% and the propagation delay is also reduced by up to 22%. Even when implemented with an ASIC chip, the hardware area is reduced by up to 35% and the delay is reduced by up to 19.2%.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.11a
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• pp.388-389
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• 2022

Recently, AI (Artificial Intelligence) has been applied to various technologies such as automatic driving, robot and smart communication. Currently, AI system is developed by software-based method using tensor flow, and GPU (Graphic Processing Unit) is employed for processing unit. However, if software-based method employing GPU is used for AI applications, there is a problem that we can not change the internal circuit of processing unit. In this method, if high-level jobs are required for AI system, we need high-performance GPU, therefore, we have to change GPU or graphic card to perform the jobs. In this work, we developed a CNN-based FPGA (Field Programmable Gate Array) chip to solve this problem.