• Journal of information and communication convergence engineering
• /
• v.14 no.3
• /
• pp.177-183
• /
• 2016

A lot of Internet of Things devices has resource-restricted environment, so it is difficult to implement the existing block ciphers such as AES, PRESENT. By this reason, there are lightweight block ciphers, such as SIMON, SPECK, and Simeck, support various block/key sizes. These lightweight block ciphers can support the security on the IoT devices. In this paper, we propose efficient implementation methods and performance results for the Simeck family block cipher proposed in CHES 2015 on an 8-bit ATmega128-based STK600 board. The proposed methods can be adapted in the 8-bit microprocessor environment such as Arduino series which are one of famous devices for IoT application. The optimized on-the-fly (OTF) speed is on average 14.42 times faster and the optimized OTF memory is 1.53 times smaller than those obtained in the previous research. The speed-optimized encryption and the memory-optimized encryption are on average 12.98 times faster and 1.3 times smaller than those obtained in the previous studies, respectively.

• Annual Conference of KIPS
• /
• 2000.10a
• /
• pp.219-222
• /
• 2000

본 논문에서는 미국 국립표준기술연구소의 AES 개발과제 추진일정 제 2라운드에서 선정된 다섯 개의 128비트 암호 알고리듬 중에서 RC6 암호 알고리듬에 대해 ALTERA FPGA를 사용하여 하드웨어로 구현한다. RC6 암호 알고리듬을 하드웨어로 구현하는 과정에서, 키 스케줄링을 포함한 경우와 포함하지 않는 경우에 대하여 각각의 모듈에 대한 구현 방법을 기술하고, 구현된 각각의 코어가 각각 5.37MHz와 5.18MHz로 동작하며, 22개의 클럭을 사용하여 암호/복호화가 완료됨을 보여준다.

• ETRI Journal
• /
• v.43 no.4
• /
• pp.746-757
• /
• 2021

Side-channel attacks pose an inevitable challenge to the implementation of cryptographic algorithms, and it is important to mitigate them. This work identifies a novel data encoding technique based on 1-of-4 codes to resist differential power analysis attacks, which is the most investigated category of side-channel attacks. The four code words of the 1-of-4 codes, namely (0001, 0010, 1000, and 0100), are split into two sets: set-0 and set-1. Using a select signal, the data processed in hardware is switched between the two encoding sets alternately such that the Hamming weight and Hamming distance are equalized. As a case study, the proposed technique is validated for the NIST standard AES-128 cipher. The proposed technique resists differential power analysis performed using statistical methods, namely correlation, mutual information, difference of means, and Welch's t-test based on the Hamming weight and distance models. The experimental results show that the proposed countermeasure has an area overhead of 2.3× with no performance degradation comparatively.

• Annual Conference of KIPS
• /
• 2020.05a
• /
• pp.180-183
• /
• 2020

물리적 정보를 이용해 암호 알고리즘의 비밀정보를 분석하는 부채널분석 분야에서도 딥러닝을 접목한 분석방법들이 활발히 제안되고 있다. 본 논문에서는 소비전력이 시간축상으로 흐트러지는 현상인 지터가 있는 파형을 신경망의 특성을 기반으로 효과적으로 분석하는 방법을 제안한다. 제안한 방법을 실험적으로 검증하기 위해 지터가 있는 AES-128 파형을 Convolutional Neural Network와 Multi-Layer Perceptron을 기반으로 분석한 결과 제안한 방법을 적용한 신경망은 모든 바이트 키 분석에 성공했으나, 이외의 신경망은 일부 혹은 모든 바이트 키 분석에 실패했다.

• Korean Journal of Materials Research
• /
• v.11 no.5
• /
• pp.361-366
• /
• 2001

It is difficult to obtain high Cu nucleation density and continuous Cu films in Cu-MOCVD without cleaning the TiN substrate prior to Cu deposition. In this study effects of plasma precleaning on the Cu nucleation density were investigated using SEM, XPS, AES, AFM analyses. Direct plasma pretreatment is much more effective than remote plasma pretreatment in enhancing Cu nucleation. Cleaning effects are enhanced with increasing the rf-power and the plasma exposure time in hydrogen plasma pretreatment. The mechanism through which Cu nucleation is enhanced by plasma pretreatment is as follows: Hydrogen ion\ulcorner in the hydrogen plasma react with TiN to form Ti and $NH_3$ Cu nucleation is easier on the Ti substrate than TiN substrate.

• Journal of the Korean Society of Systems Engineering
• /
• v.14 no.2
• /
• pp.73-82
• /
• 2018

In this work, a hardware based cryptographic module for the cyber security of nuclear power plant is developed using a system engineering approach. Nuclear power plants are isolated from the Internet, but as shown in the case of Iran, Man-in-the-middle attacks (MITM) could be a threat to the safety of the nuclear facilities. This FPGA-based module does not have an operating system and it provides protection as a firewall and mitigates the cyber threats. The encryption equipment consists of an encryption module, a decryption module, and interfaces for communication between modules and systems. The Advanced Encryption Standard (AES)-128, which is formally approved as top level by U.S. National Security Agency for cryptographic algorithms, is adopted. The development of the cyber security module is implemented in two main phases: reverse engineering and re-engineering. In the reverse engineering phase, the cyber security plan and system requirements are analyzed, and the AES algorithm is decomposed into functional units. In the re-engineering phase, we model the logical architecture using Vitech CORE9 software and simulate it with the Enhanced Functional Flow Block Diagram (EFFBD), which confirms the performance improvements of the hardware-based cryptographic module as compared to software based cryptography. Following this, the Hardware description language (HDL) code is developed and tested to verify the integrity of the code. Then, the developed code is implemented on the FPGA and connected to the personal computer through Recommended Standard (RS)-232 communication to perform validation of the developed component. For the future work, the developed FPGA based encryption equipment will be verified and validated in its expected operating environment by connecting it to the Advanced power reactor (APR)-1400 simulator.

• Journal of Acupuncture Research
• /
• v.40 no.2
• /
• pp.111-128
• /
• 2023

Trigger finger is a common cause of hand disability that results in finger catching, clicking, or locking. Conventional treatment options such as medication, injection, and surgery have limitations. Studies have indicated that acupuncture and acupotomy can be effective in treating trigger finger. However, no review regarding these treatment modalities has been published yet. This review included randomized controlled trials published until January 2023, investigating acupuncture-related interventions. The primary outcomes of interest included the effectiveness rate (ER) and pain intensity, measured using a visual analog scale (VAS) and Numerical Rating Scale (NRS), and secondary outcomes were the Quinnell grade (QG) and recurrence rate (RR). Adverse events (AEs) have also been reported wherever available. Overall, 19 studies were included, and results demonstrated that arcedge acupuncture improved the ER and QG and reduced NRS, and acupuncture was effective in reducing VAS. Compared with conventional surgery, acupotomy alone improved the ER and QG and lowered VAS and RR, with relatively fewer AEs. Acupotomy add-on treatment was more effective than conventional treatment; however, careful interpretation is needed for VAS. Acupotomy add-on treatment was more effective than acupotomy alone. However, the overall results must be interpreted with caution because of study quality, small sample size, and heterogeneity of the results.

• Journal of Broadcast Engineering
• /
• v.17 no.2
• /
• pp.374-387
• /
• 2012

In this paper, we implement a new hardware for finding the significant coefficients of a digital hologram and ciphering them using discrete wavelet packet transform (DWPT). Discrete wavelet transform (DWT) and packetization of subbands is used, and the adopted ciphering technique can encrypt the subbands with various robustness based on the level of the wavelet transform and the threshold of subband energy. The hologram encryption consists of two parts; the first is to process DWPT, and the second is to encrypt the coefficients. We propose a lifting based hardware architecture for fast DWPT and block ciphering system with multi-mode for the various types of encryption. The unit cell which calculates the repeated arithmetic with the same structure is proposed and then it is expanded to the lifting kernel hardware. The block ciphering system is configured with three block cipher, AES, SEED and 3DES and encrypt and decrypt data with minimal latency time(minimum 128 clocks, maximum 256 clock) in real time. The information of a digital hologram can be hided by encrypting 0.032% data of all. The implemented hardware used about 200K gates in $0.25{\mu}m$ CMOS library and was stably operated with 165MHz clock frequency in timing simulation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.11C
• /
• pp.1077-1087
• /
• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.6B
• /
• pp.954-961
• /
• 2010

Stream cipher was worse than block cipher in terms of security, but faster in execution speed as an advantage. However, since so far there have been many algorithm researches about the execution speed of block cipher, these days, there is almost no difference between them in the execution speed of AES. Therefore an secure and fast stream cipher development is urgently needed. In this paper, we propose a 32bit output fast stream cipher, AA32, which is composed of ASR(Arithmetic Shifter Register) and simple logical operation. Proposed algorithm is a cipher algorithm which has been designed to be implemented by software easily. AA32 supports 128bit key and executes operations by word and byte unit. As Linear Feedback Sequencer, ASR 151bit is applied to AA32 and the reduction function is a very simple structure stream cipher, which consists of two major parts, using simple logical operations, instead of S-Box for a non-linear operation. The proposed stream cipher AA32 shows the result that it is faster than SSC2 and Salsa20 and satisfied with the security required for these days. Proposed cipher algorithm is a fast stream cipher algorithm which can be used in the field which requires wireless internet environment such as mobile phone system and real-time processing such as DRM(Digital Right Management) and limited computational environments such as WSN(Wireless Sensor Network).