• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.12
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• pp.822-830
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• 2014

Recently, A Security service in Internet environments has been more important and the use of SSL & TLS is increasing for the personel homepage as well as administrative institutions. Also, IETF suggests using DTLS, which can provide a security service to constrained devices with lower CPU power and limited memory space under IoT environments. In this paper, we implement LEA(Lightweight Encryption Algorithm) algorithm and apply it to OpenSSL. The implemented algorithm is compared with other symmetric encryption algorithms such as AES etc, and it shows the superior performance in calculation speed.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.6
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• pp.1305-1317
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• 2019

Although encryption for data protection is essential in the big data platform environment of public institutions and corporations, much performance verification studies on encryption algorithms considering actual big data workloads have not been conducted. In this paper, we analyzed the performance change of AES, ARIA, and 3DES for each of six workloads of big data by adding data and nodes in MongoDB environment. This enables us to identify the optimal block-based cryptographic algorithm for each workload in the big data platform environment, and test the performance of MongoDB by testing various workloads in data and node configurations using the NoSQL Database Benchmark (YCSB). We propose an optimized architecture that takes into account.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.257-260
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm“Rijndael”. To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation the round transformation block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• ETRI Journal
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• v.29 no.6
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• pp.820-822
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• 2007

ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an area-efficient unified hardware architecture of ARIA and AES. Both algorithms have 128-bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128-bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.155-157
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• 2016

한국 표준 블록암호 알고리듬 ARIA(Academy, Research Institute, Agency)와 미국 표준인 AES(Advanced Encryption Standard) 알고리듬은 128-비트 블록 길이를 지원하고 SPN(substitution permutation network) 구조를 특징으로 가져 서로 유사한 형태를 지닌다. 본 논문에서는 ARIA와 AES를 선택적으로 수행하는 ARIA-AES 통합 프로세서를 효율적으로 구현하였다. Verilog HDL로 설계된 ARIA-AES 통합 프로세서를 Virtex5 FPGA로 구현하여 정상 동작함을 확인하였고, $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 100KHz의 동작주파수에서 합성한 결과 39,498 GE로 구현되었다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.1
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• pp.45-52
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• 2015

Since the broadcast message in satellite signals the security of the data is extremely poor compared to other communication technologies such as the broadcast signal. Thus, encryption of the communication satellite has become a very important issue, an analysis of the communication performance of a general service is always required. In this paper, In order to analyze the encrypted communication the turbo code in an IP-based satellite communication applies the code rate compatible punctured and The wireless channel in consideration of the actual satellite communication was constructed by placing a weight on the Rayleigh fading and the Rician fading two channels. Retransmission-based error control scheme were constructed in the best performance of H-ARQ Type-II, III scheme of a number of ways that are recently considered. we analyzed the effects of normal service against a satellite communication network The security services were configured with encryption algorithms AES, ARIA (CTR, CBC mode).

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.39-45
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• 2015

Satellite communication is high-speed large-capacity transmission in such a manner as to communicate with satellites in the chamber, and there is a wide area communication, but is not the security of the information. To compensate for this, AES encryption was applied to the CTR and CBC mode. Also, Blockage channel using a Markov chain to determine the impact caused by obstacles such as trees or buildings between the transmitter and the receiver was composed of Urban and Open Environment. The results of analyzing the performance of satellite communications over a high-speed link-based simulation, If applying encryption, performance of security is complementary but performance of the BER was aggravated and In the Open Environment fewer obstacles confirmed the BER performance is improved than the Urban Environment many obstacles.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.207-213
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• 2019

Recently, the importance for internet of things (IoT) security has increased enormously and hardware-based compact chips are needed in IoT communication industries. In this paper, we propose low-complexity crypto-processor that unifies advanced encryption standard (AES), academy, research, institute, agency (ARIA), and CLEFIA protocols into one combined design. In the proposed crypto-processor, encryption and decryption processes are shared, and 128-bit round key generation process is combined. Moreover, the shared design has been minimized to be adapted in generic IoT devices and systems including lightweight IoT devices. The proposed crypto-processor was implemented in Verilog hardware description language (HDL) and synthesized to gate level circuit in 65nm CMOS process, which results in 11,080 gate counts. This demonstrates roughly 42% better than the aggregates of three algorithm implementations in the aspect of gate counts.

• Journal of Internet of Things and Convergence
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• v.8 no.1
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• pp.79-85
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• 2022

Internet of Things (IoT) connects devices with various platforms, computing power, and functions. Due to the diversity of networks and the ubiquity of IoT devices, demands for security and privacy are increasing. Therefore, cryptographic mechanisms must be strong enough to meet these increased requirements, while at the same time effective enough to be implemented in devices with long-range specifications. In this paper, we present the performance and memory limitations of modern cryptographic primitives and schemes for different types of devices that can be used in IoT. In addition, detailed performance evaluation of the performance of the most commonly used encryption algorithms in low-spec devices frequently used in IoT networks is performed. To provide data protection, the binary ring uses encryption asymmetric fully homomorphic encryption and symmetric encryption AES 128-bit. As a result of the experiment, it can be seen that the IoT device had sufficient performance to implement a symmetric encryption, but the performance deteriorated in the asymmetric encryption implementation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.1-6
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• 2020

This paper proposes the design of an advanced S-Box for calculating multiplicative inverse in AES encryption process. In this approach, advanced S-box module is first designed based on composite field, and then the performance evaluation is performed for S-box with multi-stage pipelining architecture. In the proposed S-Box architecture, each module for multiplicative inverse is constructed using combinational logic for realizing both small-area and high-speed. Through logic synthesis result, the designed 3-stage pipelined S-Box shows speed improvement of about 28% compared to the conventional method. The proposed advanced AES S-Box is performed modelling at the mixed level using Verilog-HDL, and logic synthesis is also performed on Spartan 3s1500l FPGA using Xilinx ISE 14.7 tool.