• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.115-117
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• 2022

Whitebox encryption technique is a method of preventing exposure of encryption keys by mixing encryption key information with a software-based encryption algorithm. Whitebox encryption technique is attracting attention as a technology that replaces conventional hardware-based security encryption techniques by making it difficult to infer confidential data and keys by accessing memory with unauthorized reverse engineering analysis. However, in the encryption and decryption process, a large lookup table is used to hide computational results and encryption keys, resulting in a problem of slow encryption and increased memory size. In particular, it is difficult to apply whitebox cryptography to low-cost, low-power, and light-weight Internet of Things products due to limited memory space and battery capacity. In addition, in a network environment that requires real-time service support, the response delay time increases due to the encryption/decryption speed of the whitebox encryption, resulting in deterioration of communication efficiency. Therefore, in this paper, we analyze whether the AES-based whitebox(WBC-AES) proposed by S.Chow can satisfy the speed and memory requirements based on the experimental results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1332-1340
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• 2007

This paper describes an efficient hardware design of key wrap/unwrap algorithm for security layer of WiBro system. The key wrap/unwrap core (WB_KeyWuW) is based on AES (Advanced Encryption Standard) algorithm, and performs encryption/decryption of 128bit TEK (Traffic Encryption Key) with 128bit KEK (Key Encryption Key). In order to achieve m area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented by using field transformation technique. As a result, the gate count of the WB_KeyWuW core is reduced by about 25% compared with conventional LUT (Lookup Table)-based design. The WB_KeyWuW con designed in Verilog-HDL has about 14,300 gates, and the estimated throughput is about $16{\sim}22-Mbps$ at 100-MHz@3.3V, thus the designed core can be used as an IP for the hardware design of WiBro security system.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.9
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• pp.225-230
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• 2019

Recently, with the development of Internet technology, various encryption algorithms have been adopted to protect the sensing data measured by hardware devices. The Advanced Encryption Standard (AES), the most widely used encryption algorithm in the world, is also used in many devices with strong security. However, it has been found that the AES algorithm is vulnerable to side channel analysis attacks such as Differential Power Analysis (DPA) and Correlation Power Analysis (CPA). In this paper, we present a software optimization implementation technique of the AES algorithm applying the most widely known masking technique among side channel analysis attack methods.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.132-134
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• 2004

This paper proposes partial image encryption system for secure transmission of images. Partial image encryption is suitable for real-time processing purpose of multimedia data that needs compression and encryption. Compression part uses modified SPIHT algorithm and encryption part uses AES. Partial image encryption is significant reduction in encryption time in comparison with whole image encryption.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.4
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• pp.262-266
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• 2011

In high data-rate communication systems, encryption/decryption must be processed in high speed. In this paper, we implement CCM security mode which is the basis of security. Specifically, we combine CCM with AES block encryption algorithm in hardware. With the combination, we can carry out encryption/decryption as well as data transmission/reception simultaneously without reducing data-rate, and we keep low-power consumption with high speed by optimizing CCM block.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.67-74
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• 2008

A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.6
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• pp.1065-1078
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• 2014

Considering the safety of the data and performance, it can be said that the performance of the AES algorithm in a symmetric key-based encryption is the best in the IPSec-based VPN. When using the AES algorithm in IPSec-based VPN even with the expensive hardware encryption card such as OCTEON Card series of Cavium Networks, the Performance of VPN works less than half of the firewall using the same hardware. In 2008, Intel announced a set of 7 AES-NI instructions in order to improve the performance of the AES algorithm on the Intel CPU. In this paper, we verify how much the performance IPSec-based VPN can be improved when using seven sets of AES-NI instruction of the Intel CPU.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.3 no.2
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• pp.58-63
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• 2010

Cryptography is primarily a computationally intensive process. In this paper we expand AES scheme for analysis of computation time with four criteria, first is the compression of plain data, second is the variable size of block, third is the selectable round, fourth is the selective function of whole routine. We have tested our encryption scheme by c++ using MinGW GCC. Through extensive experimentations of our scheme we found that the optimal block size.

• Journal of IKEEE
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• v.18 no.2
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• pp.198-205
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• 2014

As the development of information technology, the interests in tiny applications such as wearable devices, portable devices and RFID are increased and the importance of low-area encryption circuit is emphasized. This paper proposes a compact architecture of AES-based encryption circuit suitable for tiny applications. The circuit area is reduced by minimizing storage space and sharing computation resources. The synthesized gate-level circuit using 65nm standard cell library consists of 2,241 gates and two $8{\times}16$-bit SRAMs. It can process data at a rate of 50.57Mbits per second. Therefore, the proposed encryption circuit is suitable for various applications requiring very small encryption circuit.

• Journal of Advanced Navigation Technology
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• v.23 no.5
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• pp.339-344
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• 2019

In order to prepare for the rise of data security threats caused by the information and communication technology, technology that can guarantee the stability of the data stored in the missile test set is important. For this purpose, encryption should be performed when data is stored so that it cannot be restored even if data is leaked, and integrity should be ensured even after decrypting the data. In this paper, we apply AES algorithm, which is a symmetric key cryptography system, to the missile test set, and Encrypt and decrypt according to the amount of data for each bit of each AES algorithm. We implemented the AES Rijndael algorithm in the existing inspection system to analyze the effect of encryption and apply the proposed encryption algorithm to the existing system. confirmation of suitability. analysis of capacity and Algorithm bits it is confirmed that the proposed algorithm will not affect the system operation and the optimal algorithm is derived. compared with the initial data, we can confirm that the algorithm can guarantee data undulation.