• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.460-465
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• 2007

In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB{\sim}-0.63LSB$ and $0.53LSB{\sim}-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.35-41
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• 2000

This paper describes a merged-capacitor switching (MCS) technique to improve the signal Processing speed and resolution of CMOS analog-to-digital converters (ADCs). The proposed MCS technique improves a sampling rate by reducing the number of capacitors used in conventional pipelined ADCs. The ADC capacitor mismatch can be minimized without additional power consumption, die area, and the loss of sampling rate, when the size of each unit capacitor is increased as much as the number of capacitors reduced by the MCS technique. It is verified that the ADC resolution based on the proposed MCS technique is extended further by employing a conventional commutated feedback-capacitor switching (CFCS) technique.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.193-200
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• 2014

In this paper, the prototype of one-channel gamma-ray spectroscope for automatic radiopharmaceutical systhesis system was designed and characterized. The prototype employed CZT (CdZnTe) spear detector for gamma-ray detection and employed analog-type signal processing method. A radioactive sample Co-60 was used for measuring performance of the gamma-ray spectroscope and energy spectrum is gained with bandwidth of 1173keV. The analog board is made up of SF (shaping filter) and PHA (peak and hold amplifier) for shaping CZT output signal appropriately and ADC (analog to digital converter) and FPGA (field programmable gate array) for drawing gamma-ray spectrum by counting the digitalized gamma-ray signal data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.22-28
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• 2015

This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SS-ADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SS-ADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 MHz clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 mW with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a $0.13{\mu}m$ CMOS process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.436-439
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• 2011

본 논문은 클록 보정회로를 가진 1V 2.56-GS/s 6-bit flash analog-to-digital converter (ADC) 제안한다. 제안하는 ADC 구조에서 아날로그 블록은 단일 T/H와 2단의 프리앰프, 그리고 비교기를 사용된다. 2단의 프리앰프와 비교기의 출력에 옵셋의 크기를 줄이기 위하여 저항 평균화 기법을 적용하였다. 디지털 블록은 quasi-gray rom base 구조를 사용한다. 3입력 voting 회로로 flash ADC에서 발생하기 쉬운 bubble error를 제거하였으며, 고속 동작을 위해 단일 클록을 사용하는 TSPC F/F로 구현한다. 제안하는 flash ADC는 클록 듀티 비를 조절할 수 있는 클록 보정회로를 사용한다. 클록 보정 회로는 비교기 클록 듀티 비를 조절하여 리셋 시간과 evaluation 시간의 비율을 최적화함으로 dynamic 특성을 확보한다. 제안한 flash ADC는 1V 90nm의 CMOS 공정에서 설계되었다. Full power bandwidth인 1.2 GHz 입력에 대하여 ADC 성능을 시뮬레이션을 통해 확인하였다. 설계된 flash ADC의 면적과 전력소모는 각각 $800{\times}400\;{\mu}m^2$와 193.02mW 이다.

• Fire Science and Engineering
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• v.29 no.6
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• pp.98-108
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• 2015

An integrated command system is critical for the safety of firefighters and effective work in the headquarters of a special disaster areas such as natural disaster or large man-made hazard. The integrated command system requires environmental information such as temperature, humidity, and $CO_2$ levels, as well as personal physical information such as pulse and air respirator levels. An Analog to Digital Converter (ADC) chip converts sensed information into digital signals, and a Micro Controller Unit (MCU) transmits the digital signals to a transmission board using serial communication through a Serial Peripheral Interface (SPI). The digital signals are saved in a transmission board and transmitted to the integrated command system by a Radio Frequency (RF) unit. The location of fire-fighters in a building are determined using a gyro sensor and an inertial sensor. The collected information is applied to the integrated command system for firefighter safety and to ensure that they can effectively carry out their duties. Tthis study theoretically and experimentally investigated the technologies of RF transmission, indoor position, and an integrated command system that supports decision making using the transmitted information.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12C
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• pp.1131-1137
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• 2009

In this paper, a resource management technique for digital duplexing (DD) systems using orthogonal frequency division multiple access (OFDMA) is proposed. The proposed technique can reduce the dynamic range of the signal received at the subscriber station (SS) and minimize the effects of inter-symbol interference (ISI) and inter-carrier interference (ICI) due to the time difference of arrival (TDoA) without using a cyclic suffix. It is shown by computer simulation that the proposed technique can reduce the number of bits for an analog-to-digital converter (ADC) and increase the signal-to-interference and noise ratio (SINR) significantly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.114-121
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• 2005

In this paper, Pipelined A/D converter with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB\;and\;0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.8-15
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• 1997

In this paper, a real-time operating Motion Picture Experts Group-1 (MPEG-1) audio encoder system is implemented using a TMS320C31 Digital Signal Processor (DSP) chip. The basic operation of the MPEG-1 audio encoder algorithm based on audio layer-2 and psychoacoustic model-1 is first verified by C-language. It is then realized using the Texas Instruments (Tl) assembly in order to reduce the overall execution time. Finally, the actual BSP circuit board for the encoder system is designed and implemented. In the system, the side-modules such as the analog-to-digital converter (ADC) control, the input/output (I/O) control, the bit-stream transmission from the DSP board to the PC and so on, are utilized with a field programmable gate array (FPGA) using very high speed hardware description language (VHDL) codes. The complete encoder system is able to process the stereo audio signal in real-time at the sampling frequency 48 kHz, and produces the encoded bit-stream with the bit-rate 192 kbps. The real-time operation capability of the encoder system and the good quality of the decoded sound are also confirmed using various types of actual stereo audio signals.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1444-1445
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• 2008

최근 Wireless Local Area Network(WLAN), Wide-band Code Division Multiple Access(WCDMA), CDMA2000, Bluetooth 등 다양한 모바일 통신 시스템에 대한 수요가 증가하고 있다. 이와 같은 모바일 통신 시스템에는 70dB이상의 SFDR(Spurious Free Dynamic Range)을 가진 ADC(Analog-to-Digital Converter)가 사용된다. 본 논문에서는 모바일 통신 시스템을 위한 SFDR 70dBc의 성능을 제공하는 10비트, 100Msps 파이프라인 ADC를 제안한다. 제안한 ADC는 요구되는 해상도 및 속도 사양을 만족시키기 위해 3단 파이프라인 구조를 채택하였으며, 입력단 SHA(Sample and Hold)회로에는 Nyquist 입력에서도 10비트 이상의 정확도로 신호를 샘플링하기 위해 부트스트래핑 기법 기반의 샘플링 스위치를 적용하였다. residue amplifier 회로에는 전력을 줄이기 위해 8배 residue amplifier 대신 3개의 2배 ressidue amplifier를 사용하였다. ADC의 높은 사양을 만족시키기 위해서는 높은 이득을 가지는 op-amp가 필수적이다. 제안한 ADC 는 0.18um CMOS 공정으로 설계되었으며, 100Msps의 동작 속도에서 70dBc 수준의 SFDR과 60dB 수준의 SNDR(Signal to Noise and Distortion Ratio)을 보여준다.