• Journal of Biomedical Engineering Research
• /
• v.39 no.5
• /
• pp.220-228
• /
• 2018

The internal resistance of microbial fuel cell (MFC) using stainless steel skein for oxidizing electrode was investigated and the factors affecting the voltage generation were identified. We also investigated the effect of power management system (PMS) on the usability for MFC and the removal efficiency of organic pollutants. The performance of a stack microbial fuel cell connected with (PMS) or PMS+LED was analyzed by the voltage generation and organic matter reduction. The maximum power density of the unit cells was found to be $5.82W/m^3$ at $200{\Omega}$. The maximum current density was $47.53A/m^3$ without power overshoot even under $1{\Omega}$. The ohmic resistance ($R_s$) and the charge transfer resistance ($R_{ct}$) of the oxidation electrode using stainless steel skein electrode, were $0.56{\Omega}$ and $0.02{\Omega}$, respectively. However, the sum of internal resistance for reduction electrode using graphite felts loaded Pt/C catalyst was $6.64{\Omega}$. Also, in order to understand the internal resistance, the current interruption method was used by changing the external resistance as $50{\Omega}$, $300{\Omega}$, $5k{\Omega}$. It has been shown that the ohm resistance ($R_s$) decreased with the external resistance. In the case of a series-connected microbial fuel cell, the reversal phenomenon occurred even though two cells having the similar performance. However, the output of the PMS constantly remained for 20 hours even when voltage reversal occurred. Also the removal ability of organic pollutants (SCOD) was not reduced. As a result of this study, it was found that buffering effect for a certain period of time when the voltage reversal occurred during the operation of the microbial fuel cell did not have a serious effect on the energy loss or the operation of the microbial fuel cell.

• Journal of IKEEE
• /
• v.21 no.4
• /
• pp.388-396
• /
• 2017

Since there are many variables such as various poses, illuminations and occlusions in a face detection problem, a high performance detection system is required. Although CNN is excellent in image classification, CNN operatioin requires high-performance hardware resources. But low cost low power environments are essential for small and mobile systems. So in this paper, the CPU-FPGA integrated system is designed based on 3-stage cascade CNN architecture using small size FPGA. Adaptive Region of Interest (ROI) is applied to reduce the number of CNN operations using face information of the previous frame. We use a Field Programmable Gate Array(FPGA) to accelerate the CNN computations. The accelerator reads multiple featuremap at once on the FPGA and performs a Multiply-Accumulate (MAC) operation in parallel for convolution operation. The system is implemented on Altera Cyclone V FPGA in which ARM Cortex A-9 and on-chip SRAM are embedded. The system runs at 30FPS with HD resolution input images. The CPU-FPGA integrated system showed 8.5 times of the power efficiency compared to systems using CPU only.

• Proceedings of the Korean Society for Agricultural Machinery Conference
• /
• 2000.11c
• /
• pp.819-826
• /
• 2000

This study was performed to develop a measurement system of tractor field performance for plow and rotary operations. Measurement system for tractor consisted of torque sensors to measure torque of drive axles and PTO axle, speed sensors to measure rotational speed of drive axles and engine, microcomputer to control data logger, and data logger as I/O interface system. The measurement system was installed on four-wheel-drive tractor. Four-element full-bridge type strain gages were used for torque measurement of drive axles and optical encoders were used to measure speeds of drive axles and engine. Slip rings were mounted on the rotational axles. Signals from sensors were inputted to data logger that was controlled by microcomputer with parallel communication. Sensors were calibrated before the field tests. Regression equations were found on completion of the calibrations. The field experiment was performed at paddy fields and uplands. Rotary and plow were used when the tractor was operated in the field. Travelling speeds of the tractor were 1.9 km/h, 2.7 km/h, 3.7 km/h, 5.5 km/h, 8.2 km/h, and 11.8 km/h. Operating depths of implements were maintained approximately 20cm during the tests. Torque data of drive axles were different at each location during plow and rotary operations. Results showed that torque of rear axles were greater than those of front axles. Total torque were 6860 - 11064 Nm at the upland and 7360 - 14190 Nm at the paddy field for plow operations. It was found that torque at the paddy field were about 20% greater than those at the upland for plow operations. Torque data showed that rotary operations required less power than plow operation at the paddy field and the upland. Torque measurements at each axle for rotary operations were only 8 - 16% of plow operations in the upland and 15 - 20% in the paddy field.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 1993.06a
• /
• pp.975-976
• /
• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Korean Journal of Fisheries and Aquatic Sciences
• /
• v.34 no.6
• /
• pp.643-651
• /
• 2001

Paddlewheel-driven circulation in a culture pond has been simulated based on the depth integrated 2 dimensional hydrodynamic model. Acceleration by paddlewheel is expressed as shaft force divided by water mass discharged by paddlewheel blades. The model has been calibrated and applied to culture ponds as following steps:- i) The model predicted velocities at every 10 m along longitudinal direction from the paddlewheel. The model was calibrated comparing the results with the measured values at mass correction factor $\alpha$ and dimensionless eddy viscosity constant $\gamma$, respectively, in a range $15\~20$ and 6. ii) Wind shear stress was simulated under conditions of direction $0^{\circ}C,\;90^{\circ}C\;and\;180^{\circ}C$ and speed 0.0, 2.5, 5.0 and 7.5 m/s. Change rate of current speed was <$1\%$ at wind in parallel or opposite direction to the paddlewheel-driven jet flow, while $4\%$ at orthogonal angle. iii) The model was then applied to 2 culture ponds located at the Western coast of Korea. The measured and predicted currents for the ponds were compared using the regression analysis. Analysis of flow direction and speed showed correlation coefficients 0.8928 and 0.6782 in pond A, 0.8539 and 0.7071 in pond B, respectively. Hence, the model is concluded to accurately predict circulation driven by paddlewheel such that it can be a useful tool to provide pond management strategy relating to paddlewheel operation and water quality.