• Title/Summary/Keyword: A Boolean function

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The Development of PLD Design Tool using the EDIF Netlist (EDIF Netlist를 이용한 PLD 설계용 툴 개발)

  • Kim, Hi-Seok;Byun, Sang-Zoon
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.4
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    • pp.1025-1032
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    • 1998
  • In this paper, the PLD design tool which realizes a digital circuit as PLD, by using EDIF netlist of the digital circuit designed at OrCAD have been developed. This paper is proposed the following algorithms: JIE(Joined Information Extractor) which extracts the connecting information between both cells in order to realize the digital circuit as PLD using the EDIF netlist, FND(Feedback Node Detector) which look into whether feedback exists or not, BEG(Boolean Equation Generator) which generates a boolean equation, and so on. Also, this paper is developed auto-select function which selects the PLD element with consideration of number of I/O variables of the minimized boolean equation, and algorithm generation JEDEC file of GAL6001 and GAL6002, having a forms of EPLD which is bigger than PLD.

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Design of a Technology Mapping System for Logic Circuits (논리 회로의 기술 매핑 시스템 설계)

  • 김태선;황선영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.29A no.2
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    • pp.88-99
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    • 1992
  • This paper presents an efficient method of mapping Boolean equations to a set of library gates. The proposed system performs technology mapping by graph covering. To select optimal area cover, a new cost function and local area optimization are proposed. Experimental results show that the proposed algorithm produces effective mapping using given library.

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Full-Round Differential Attack on the Original Version of the Hash Function Proposed at PKC'98 (PKC'98에 제안된 해쉬 함수의 Original Version에 대한 전체 라운드 차분 공격)

  • 장동훈;성재철;이상진;임종인;성수학
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.12 no.2
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    • pp.65-76
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    • 2002
  • Shin et al. proposed the new hash function with 160-bit output length at PKC'98. This hash function is based on the advantages of the existing hash functions, such as SHA-1, RIPEMD-160, HAVAL, and etc.$^{[1]}$ Recently, Han et al. cryptanalyzed the hash function proposed at PKC'98 and proposed the method finding a collision pair with $2^{-30}$ probability at FSE 2002, supposing that boolean functions satisfy SAC(Strict Avalanche Criterian).$^{[2]}$ This paper improves the method and shows that we can find a collision pair from the original version of the hash function with $2^{-37.13}$ probability through the improved method. And we point out that the problem of the function comes from shift values dependent on message.

Error Detection using Advanced Parity Bit (패리티 비트를 확장한 오류 검사에 관한 연구)

  • Kim, In-Soo;Min, Hyoung-Bok;Kim, Yong-Hyun;Kim, Shin-Taek
    • Proceedings of the KIEE Conference
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    • 2008.07a
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    • pp.1965-1966
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    • 2008
  • The manipulation of Boolean functions is a fundamental part of computer science, and many problems in the design and testing of digital systems can be expressed as a sequence of operations. It is mainly a paper of our research on the techniques of Boolean function manipulation using Binary Decision Diagram(BDDs) and their applications for VLSI CAD System. In many practical applications related to digital system design, it is a basic technique to use ternary-valued functions. In this paper, we discuss the methods for representing logical values.

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Optical Look-ahead Carry Full-adder Using Dual-rail Coding

  • Gil Sang Keun
    • Journal of the Optical Society of Korea
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    • v.9 no.3
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    • pp.111-118
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    • 2005
  • In this paper, a new optical parallel binary arithmetic processor (OPBAP) capable of computing arbitrary n-bit look-ahead carry full-addition is proposed and implemented. The conventional Boolean algebra is considered to implement OPBAP by using two schemes of optical logic processor. One is space-variant optical logic gate processor (SVOLGP), the other is shadow-casting optical logic array processor (SCOLAP). SVOLGP can process logical AND and OR operations different in space simultaneously by using free-space interconnection logic filters, while SCOLAP can perform any possible 16 Boolean logic function by using spatial instruction-control filter. A dual-rail encoding method is adopted because the complement of an input is needed in arithmetic process. Experiment on OPBAP for an 8-bit look-ahead carry full addition is performed. The experimental results have shown that the proposed OPBAP has a capability of optical look-ahead carry full-addition with high computing speed regardless of the data length.

On the Minimization of the Switching Function by the MASK Method (MASK 방법에 의한 이론함수의 최소화)

  • 조동섭;황희융
    • 전기의세계
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    • v.28 no.11
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    • pp.37-44
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    • 1979
  • This paper deals with the computer program of finding the minimal sum-of-products for a switching function by using the MASK method derived from the characteristics of the Boolean algebra. The approach differs from the previous procedures in that all the prime implicants are determined only by the bit operation and the minimal sum-of-products are obtained by the modified Petrick method in this work. The important features are the relatively small amount of the run time and the less memory capacity to solve a problem, as compared to the previous computer programs.

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On the Computerization of Minimizing the Switching Function by the MASK Method

  • Cho, Dong-Sub;Hwang, Hee-Yeung
    • Proceedings of the KIEE Conference
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    • 1979.08a
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    • pp.69-72
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    • 1979
  • This paper deals with the computer method of finding the minimal sum of products for a switching function by using the MASK method derived from the characteristics of the Boolean algebra. The experiments with the program which is dissimilar to the previous computer programs show that the algorithm presented will be more efficient.

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Output Phase Assignment Algorithm for Multilevel Logic Synthesis (다단 논리합성을 위한 출력 Phase 할당 알고리즘)

  • 이재흥;정종화
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.10
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    • pp.847-854
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    • 1991
  • This paper presents a new output phase assignment algorithm which determines the phases of all the nodes in a given boolean network. An estimation function is defined, which is represented by the relation between the literals in the given function expression. A weight function, WT (fi, fj) is defined, which is represented by approximate amount of common subexpression between function fi and fj. Common Subexpression Graph(CSG) is generated for phase selection by the weight function between all given functions. We propose a heuristic algorithm finding subgraph of which sum of weights has maximum by assigning phases into the given functions. The experiments with MCNC benchmarks show the efficiency of the proposed method.

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Analysis and Implementation of Linear Combination of Weighted Order Statistic Filters (Linear Combination of Weighted Order Statistic 필터의 분석과 구현)

  • 송종환;이용훈
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.2
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    • pp.21-27
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    • 1994
  • Linear combination of weighted order statistic(LWOS) filters, which is an extension of stack filters, can represent any Boolean function(BF) or its extension. Which is called the extended BF(EBF). In this paper, we present a procedure for finding an LWOS filter of the simplest type from LWOS filters which are equivalent to a given BF or EBF. In addition, a property that is useful for implementing an LWOS filter is derived and an algorithm for LWOS filtering is presented.

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Development of Smart CAD/CAM System for Machining Center Based on B-Rep Solid Modeling Techniques (I) (A Study on the B-Rep Solid Modeler using Half Edge Data Structure) (B-Rep 솔리드모델을 이용한 머시닝 센터용 CAC/CAM 시스템 개발(1): 반모서리 자료구조의 B-Rep 솔리드모델러에 관한 연구)

  • 양희구;김석일
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1994.10a
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    • pp.689-694
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    • 1994
  • In this paper, to develop a smart CAD/CAM system for systematically performing from the 3-D solid shape design of products to the CNC cutting operation of products by a machining center, a B-Rep solid modeler is realized based on the half edge data structure. Because the B-Rep solid modeler has the various capabilities related to the solid definition functions such as the creation operation of primitives and the translational and rotational sweep operation, the solid manipulation functions such as the split operation and the Boolean set operation, and the solid inversion function for effectively using the data structure, the 3-D solid shape of products can be easily designed and constructed. Also, besides the automatic generation of CNC code, the B-Rep solid modeler can be used as a powerful tool for realizing the automatic generation of finite elements, the interference check between solids, the structural design of machine tools and robots and so on.

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