• Journal of Power Electronics
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• 제7권3호
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• pp.222-232
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• 2007

This paper presents the application of a single phase AC-to-DC converter using a three-phase series parallel (SPRC) resonant converter to variable speed dc-drive. The improved power quality converter gives the input power factor unity over a wide speed range, reduces the total harmonic distortion (THD) of ac input supply current, and makes very low ripples in the armature current and voltage waveform. This soft-switching converter not only possesses the advantages of achieving high switching frequencies with practically zero switching losses but also provides full ranges of voltage conversion and load variation. The proposed drive system is the most appropriate solution to preserve the present separately excited de motors in industry compared with the use of variable frequency ac drive technology. The simulation and experimental results are presented for variable load torque conditions. The variable frequency control scheme is implemented using a DSP- TMS320LF2402. This control reduces the switching losses and current ripples, eliminates the EMI and improves the efficiency of the drive system. Experimental results confirm the consistency of the proposed approach.

• Journal of Power Electronics
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• 제5권4호
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• pp.247-256
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• 2005

In order to harvest power in an efficient manner from a micro piezoelectric (PZT) device for charging the battery of a remote system, a new AC/DC resonant pulse power converter is proposed. The proposed power converter has two stages in the power conversion process. The first stage includes N-type MOSFET full bridge rectifier. The second stage includes a boost converter having an N-type MOSFET and a P-type MOSFET. MOSFETs work in the $1^{st}$ or $3^{rd}$ quadrant region. A small inductor for the boost converter is assigned in order to make the size of the power converter as small as possible, which makes the on-interval of the MOSFET switch of the boost converter ultimately short. Due to this short on-interval, the parasitic junction capacitances of MOSFETs affect the performance of the power converter system. In this paper, the performance of the new converter is analytically and experimentally evaluated with consideration of the parasitic capacitance of switching devices.

• 전자공학회논문지
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• 제50권10호
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• pp.91-97
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• 2013

본 논문에서는 NTSC/PAL 아날로그 TV를 구동하기 위한 10-bit current steering D/A 변환기를 제안하였다. 제안하는 D/A 변환기는 50MS/s 의 동작속도를 가지며, 6+4 분할 구조로 설계되었다. 또한 새로운 개념의 자가보정 바이어스 기법을 적용하여 칩 내부의 종단저항을 사용하고도 공정오차를 최소화 하였다. 제안하는 D/A 변환기는 3.3V 0.11um 1-poly 6-metal CMOS 공정을 사용하여 제작되었다. 제작된 칩의 유효 면적은 $0.35mm^2$, 3.3V 전원전압 상에서 약 88mW의 전력소모를 나타내었다. 실험 결과는 변환 속도 50MS/s, 입력 주파수 1MHz에서 SFDR 63.1dB의 특성을 나타내었다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.394-395
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• 2011

In order to increase the power conversion efficiency and improve the power factor, a modified forward converter is proposed, which adopts a capacitive output filter instead of the inductive output filter of the conventional forward converter. Therefore, the proposed converter has wide input voltage range in opposite to that of the conventional forward converters. Moreover, the proposed converter uses the critical conduction mode for automatic current shaping to improve the power factor. As a result, the proposed converter can achieve quasi-resonant zero-voltage-switching, which can minimize the switching loss of main MOSFET. In addition, the operational principle of the proposed converter is analyzed and the characteristic of the proposed converter is investigated in this paper. To validate the effectiveness of the proposed converter, a prototype of 13W is implemented and the experimental results are discussed in more detail.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.246-251
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• 2014

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

• 한국산학기술학회논문지
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• 제14권2호
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• pp.840-845
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• 2013

본 논문에서는 LC 필터 기술을 기반으로 하는 광대역 주파수 이중 하향변환기(Frequency Double Down-Converter)를 설계 및 제작하였다. 설계한 이중 하향변환기는 저잡음 증폭기, 혼합기, IF 증폭기, LC 필터 등으로 구성되며, DC-Block 커패시터와 RF-Bypass 커패시터로 구성된다. 설계 시에 기존 변환기의 능동소자를 수동소자로 구현하였으며 이에 따라 전력감소 및 저가의 비용을 실현할 수 있었다. 측정 결과, 제작한 주파수 이중 하향변환기는 중심 주파수 63MHz 에서 대역폭 100MHz (13~113MHz)인 광대역을 실현하였으며, 이득은 약 40dB 임을 확인하였다.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.1944-1953
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• 2014

This paper shows the design and control methods of the bidirectional DC-DC converter to generate the proper DC-link voltage of a PMSM drive. Conventionally, because the controllable power of the PWM based voltage source inverter is limited by its DC-link voltage, the DC-DC converter is used for boosted DC-link voltage if the inverter source cannot generate enough operating voltage for the PMSM drive. In this paper, to obtain more utilization of this DC-DC converter, optimal DC-link voltage control for PMSM drive will be explained. First, the process and current path of the DC-DC converter will be illustrated, and a control method of this converter for variable DC-link voltage will then be explained. Finally, an improvement analysis of the optimal DC-link voltage control method, especially on the deadtime effect, will be explained. The DC-DC converter of the proposed control method is verified by the experiments by comparing with the conventional constant voltage control method.

• 전자공학회논문지C
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• 제36C권9호
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• pp.13-19
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• 1999

본 논문에서는 1mW의 낮은 전력소모를 갖는 8-bit 100KSPS CMOS A/D 변환기를 설계, 제작하였다. Cyclic 구조를 갖는 A/D 변환기에서 발생하는 연산증폭기의 시스템적인 offset 전압을 효과적으로 감소시키기 위해, 새로운 시스템적인 offset 전압 제거 기술을 제안하였다. 또한 기존 Gain 증폭기에서 발생하는 오차를 감소시키기 위해 완전 차동 구조의 Gain 증폭기를 설계하였다. 제안된 A/D 변환기는 $0.6{\mu}m$ single-poly triple-metal n-well CMOS 공정을 사용하여 제작되었으며, +3V 단일 공급전압에서 DNL과 INL은 ${\pm}1LSB$ 이내로 측정되었고, 100KHz의 샘플링 주파수에서 43dB의 SNR를 갖는다. 측정된 최대전력소모는 $980{\mu}W$로 나타났다.

• 전기학회논문지
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• 제56권2호
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• pp.301-310
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• 2007

Bidirectional DC-DC converters allow transfer of power between two dc sources, in either direction. Due to their ability to reverse the direction of flow of power, Dey are being increasingly used in many applications such as battery charge/dischargers, do uninterruptible power supplies, electrical vehicle motor drives, aerospace power systems, telecom power supplies, etc. This Paper Proposes a new bidirectional Sepic/Zeta converter. It has low switching loss and low conduction loss due to auxiliary communicated circuit and synchronous rectifier operation, respectively Because of positive and buck/boost-like DC voltage transfer function(M=D/1-D), the proposed converter is very desirable for use in distributed power system. The proposed converter also has both transformer-less version and transformer one.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1679-1685
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• 1989

In this paper, a new design of GaAs level converter is proposed, and anlyzed wth the variation of the threshold voltage of E/D MESFETs. The threshold voltage ranges analyzed are -0.05V to 0.35V for enhancement type MESFETs and -0.3V to -0.7V for depletion type MESFETs. In this range, the variation of the input characteristics of the conventional level converter designed to convert the level of DCFL using Vss of -0.8V to that of -0.2V, is greather than 600mV, but of the level converter proposed here is less than 100mV.