• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.164-167
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• 2000

This paper introduces the design of high-speed analog-to-digital converter for hard disk drive (HDD) read channel. This is based on autozero technique for low-error rate, and Double Speed Dual ADC(DSDA) technique lot efficiently increasing the conversion speed of A/D converter. This An is designed by 6bit resolution, 800M sample/s maximum conversion rate, 390㎽ power dissipation, one clock cycle latency in 0.65 $\mu\textrm{m}$ CMOS technology.

• Journal of Industrial Technology
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• v.29 no.B
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• pp.145-149
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• 2009

A RF-DC converter is one of the most important components for a wireless power transmission. It has been developed for many applications such as space solar power system, and Radio Frequency Identification(RFID). In this paper, we designed three types of RF-DC converter and compare the performance of each. All types RF-DC convertoer have a maximum conversion efficiency at input power level of 0 dBm~5 dBm and RF-DC converter of third type was the best performance that has a 21.9% of conversion efficiency.

• Journal of Sensor Science and Technology
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• v.8 no.2
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• pp.163-170
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• 1999

A programmable A/D converter for an embedded fiber-optic combustion pressure sensor has been designed with 8 N and P channel MOSFETs, respectively. A local field enhancement for reducing programming voltage during writing as well as erasing an EEPROM device is introduced. In order to observe linear programmability of the EEPROM device during programming mode, a cell is developed with a $1.2\;{\mu}m$ double poly CMOS fabrication process in MOSIS. It is observed that the high resolution, of say 10mVolt, is valid in the range 1.25volts to 2volts. The experimental result is used for simulating the programmable 8 bit A/D converter with Hspice. The A/D converter is demonstrated to consume low power, $37\;{\mu}W$ by utilizing a programming operation. In addition, the converter is attained at the conversion frequency of 333 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.43-49
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• 2004

In this paper, we have designed a mode size converter to reduce coupling loss between super-high delta silica optical waveguides and single mode fibers. The new mode size converter has three design aspects; periodically segmented taper waveguide for minimal size, lateral taper waveguide for simple fabrication, and surrounding trenches to improve coupling loss. In the optimal mode size converter design, coupling loss is 0.33dB/point without trenches and 0.2dB/point with trenches.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.5
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• pp.3079-3085
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• 2014

This paper suggests a power level controllable frequency up-converter which is designed and fabricated using both the filtering technology consisted with only passive devices and a multi-level digital attenuator. The suggested frequency up-converter simultaneously realizes the low power consumption and the low cost model. Because of the possibility for controlling power levels, it is possible to use the suggested frequency up-converter for wide spectral range. According to the experimental results, the average gain value of 0.75dB is obtained for the bandwidth of 160MHz at the center frequency of 1,200MHz. Especially, it is confirmed that the power level can be controlled from 10 to -21.5dBm through the digital attenuator.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.131-134
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• 2002

In this work, we have developed a systematic way of utilizing the basic design tools for superconductive electronics. This include WRSPICE, XIC, margin program, and L-meter. Since the high performance analog-to- digital converter can be built with Rapid Single Flux Quantum (RSFQ) logic circuits the development of superconductive analog-to-digital converter has attracted a lot of interests as one of the most prospective area of the application of Josephson Junction technology. One of the main advantages in using Rapid Single Flux Quantum logic in the analog-to-digital converter is the low voltage output from the Josephson junction switching, and hence the high resolution. To design an 1-bit analog-digital converter, first we have used XIC tool to compose a circuit schematic, and then studied the operational principle of the circuit with WRSPICE tool. Through this process, we obtained the proper circuit diagram of an 1-bit analog-digital converter circuit. Based on this circuit we performed margin calculations of the designed circuits and optimized circuit parameters. The optimized circuit was laid out as a mask drawing. Inductance values of the circuit layout were calculated with L-meter. Circuit inductors were adjusted according to these calculations and the final layout was obtained.

• The Transactions of the Korea Information Processing Society
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• v.2 no.1
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• pp.66-74
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• 1995

A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at ＋5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high- speed, low-power consumption, small area applications and one-chip mixed Analog- Digital system. Simulations are performed with PSPICE and a fabricated chip is tested.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1A
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• pp.85-90
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• 2008

Effects of the emitter degeneration on linearity have been investigated in SiGe HBT double-balanced up-converters with the Gilbert-cell structure. The emitter-coupled degeneration resistors have been optimized for high P1-dB and IP3 through the nonlinear harmonic-balance simulation. Two types of up-converter MMICs fabricated in $0.35{\mu}m$ Si-BiCMOS process were measured to verify the simulation results. The up-converter without the degeneration resistors produces a P1-dB of -13 dBm with an OIP3 of 3.7 dBm, while the up-converter with the degeneration resistors produces a P1-dB of -10 dBm with an OIP3 of 8.7 dBm.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.4
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• pp.346-352
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• 2002

A novel Zero Current Switching(ZCS) Pulse Width Modulation(PWM) boost converter with dual mode for reducing two rectifiers reverse recovery related losses is proposed. The switches of the proposed converter are operating to work alternatively turn-on and turn-off with soft switching condition In the every cycle and the proposed converter reduces the reverse recovery current, which is related switching losses and EMI problems, of the free-wheeling diode$(D_1, D_2)$ by adding the resonant inductor Lr, in series with the switch $S_1$. The switching components$(S_1, S_2, D, D_1)$ in the proposed boost converter are subjected to minimum voltage and current stresses same as those in their PWM counterparts because there are no additional active switches and resonant elements compared with the conventional ZVT PWM $converters^{[2]}$. The operation of the proposed converter, in this paper, is analyzed and to verify the feasibility of the characteristics is built and tested.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.793-797
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• 2003

Switching PFC converters are widely used not only to comply the power quality specification but also for maximum efficiency. However switching PFC converters generate serious electromagnetic interference (EMI). In this paper to solve this problem, we applied the APW(Anti Phase Winding) and RPWM(Ran-dom PWM) technique to PFC boost converter and obtained satisfactory results. Simulation and experimental results show the improved harmonic and reduced EMI effect in air-conditioner system.