• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.246-251
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• 2014

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.11
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• pp.1125-1130
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• 2017

The tooth shapes of serration-type and spline-type reactors are optimized using finite element methods to improve the working life of the part and to lower the stress concentration during rotation resulting from contact with the outer race for a reactor operating with $170^{\circ}C$ transmission oil. The results of thermal expansion analyses between an Al reactor and the steel outer race indicate that, before optimization, the gap between the two parts increases further as the serration-type reactor expands by 0.1 mm and the spline-type one strains by 0.08 mm. Because of shape optimization, a trapezoidal shape is obtained from the initial triangular serration and the rectangular spline of the two reactors. The maximum von Mises stress of the serration-type convertor decreased by 24.5 ％, and by 9.3 ％ for the spline-type convertor. In addition, there is a 13 ％ reduction in the axial thickness, as compared to the initially designed model.

• Journal of electromagnetic engineering and science
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• v.13 no.3
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• pp.189-191
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• 2013

This letter presents a compact metamaterial-based tunable zeroth-order resonant antenna. It is based on the double-negative unit cell with a function of tunable inductance realized by a varactor and impedance convertor in the shunt branch. The resonant frequency of the designed antenna ranges from 2.31 to 3.08 GHz, depending on the capacitance of the used varactor. Its size is very compact ($0.05{\lambda}_0{\times}0.2{\lambda}_0$) with a relatively wide tunable range of 29.1%. The impedance bandwidth of the antenna is from 20 to 50 MHz for the resonant center frequency. The measured maximum total realized gain is from -0.68 dBi (2.43 GHz) to 1.69 dBi (2.97 GHz). The EM-simulated and measured results are in good agreement.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.3
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• pp.433-437
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• 2015

We have designed and fabricated a low power and high linearity up down convertor for wireless repeaters using $0.35{\mu}m$ SiGe Bipolar CMOS technology. Repeater is composed of a wideband up/down converting mixer, programmable gain amplifiers (PGA), input buffer, LO buffer, filter driver amplifier and integer-N phase locked loop (PLL). As of the measurement results, OIP3 of the down conversion mixer and up conversion mixer are 32 dBm and 17.8 dBm, respectively. The total dynamic gain range is 31 dB with 1 dB gain step resolution. The adjacent channel leakage ratio (ACLR) is 59.9 dBc. The total power consumption is 240 mA at 3.3 V.

• KSBB Journal
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• v.13 no.4
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• pp.461-467
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• 1998

A fermentation system was supplemented with a device for the measurement of the durations of alkali pump feeding for automatic pH control and an A/D convertor for precise monitoring of pH value by computer. A software program was developed to measure buffer capacities from the pH signal and the pH control signal during fermentation. By measuring the buffer capacity on-line, levels of acetic acid were estimated by a software sensor using pH signal in a fermentation process of E.coli growing in a minimal medium. The measured values of acetic acid showed correlation to those of estimated by the software sensor. Lacitic acid production was also successfully estimated by the values of buffer capacities measured on-line.

• Proceedings of the Safety Management and Science Conference
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• 2004.05a
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• pp.241-245
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• 2004

In this paper, we implement a portable bioelectric signal measurement system for the safety of industrial workers. The developed system consists of two parts: the one is boielectric signal measurement unit and the other is signal analyzer system with PDA. The former includes signal processing part, A/D convertor, and 8051 based microprocessor, the latter includes software for signal analysis and display. The developed system detects industrial worker's ECG and displays and stores it to PDA. The ECG data in PDA can be transmitted to PC located in a distance, allowing a doctor to review the ECG and make a treatment decision. A doctor analyzes the ECG data and gives medical treatment to industrial worker.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1983-1993
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• 1993

A power-reduction technique for full-flash A/D converters is proposed. As the resolution of a full-flash A/D converter increases linearly, the number of comparators increases exponentially. The power dissipation is generally larger than other A/D converter architectures because there are many comparators, and they are operating continuously. In this proposed architecture, only a selected number of conmarators are made to operate instead of activating all the comparators of the full-flash A/D convertor. To determine whichcomparators should be activated, voltage levelfider circuits are used. A new clock driver is developed to suppress the dynamic glitch noise which is fed back into the input stage of the comparator. By using this clock driver, the glitch noise in the current source is reduced to one fourth of that when the typical clock signal is applied. The proposed architecture has been implemented with 1.2 m 5GHz BiCMOS technology. The maximum conversion speed is 350Msamples/s. and dissipates only 900mW.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.2
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• pp.13-19
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• 2012

The techniques of 3d image processing have broadly used in the areas including movies, games, performances, exhibitions. In addition, increasing demands for practical uses have gradually extended to the areas of architecture, medicine, nuclear power plant. However, dominant techniques for 3d image processing seem to depend on multi-camera in which two stereo images are merged into one image. Also the pipeline has limitations to provide real-time 3d viewer in ubiquitous computing. It is not able to be applicable onto most general screens as well. In addition, the techniques can be utilized for the real-time 3d game play without a particular monitor or convertor. Hence, the research presented here is to aim at developing an efficient real-time 3d viewer using only mono camera which do not need post processing for editing as well.

• Proceedings of the KIEE Conference
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• 2002.07a
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• pp.187-189
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• 2002

A relaying board is developed for the study of digital relay, which is based on Digital Signal Processor(DSP). The present development is capable of understanding and application for digital relay hardware. To support the design of relaying hardware, first A/D convertor MMI and serial port for communication are embedded, and next a booting cables of three types are supplied. More particularly the relaying board that is convinient to test digital relaying algorithm. This paper concludes by implementing the distance relaying algorithm into a relaying board, the hardware test results show practically high performance.

• Journal of electromagnetic engineering and science
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• v.17 no.1
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• pp.39-43
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• 2017

In this paper, a systematic and statistical calibration technique was implemented to calibrate a high-speed signal converting system containing multiple digital-to-analog converters (DACs). The systematic error (especially the imbalance between DACs) in the current combining network of the multi-DAC system was modeled and corrected by calculating the path coefficients for individual DACs with wideband reference signals. Furthermore, by applying a Kalman filter to suppress noise from quantization and clock jitter, accurate coefficients with minimum noise were identified. For correcting an arbitrary waveform generator with two DACs, a co-simulation platform was implemented to estimate the system degradation and its corrected performance. Simulation results showed that after correction with 4.8 Gbps QAM signal, the signal-to-noise-ratio improved by approximately 4.5 dB and the error-vector-magnitude improved from 4.1% to 1.12% over 0.96 GHz bandwidth.