• Journal of Korea Society of Industrial Information Systems
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• v.20 no.6
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• pp.21-27
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• 2015

We analyze the problem that is occurring when using parity mode transformation required for 9 bit serial communication under Linux environment and propose the solution. The parity mode change is used for 9 bit serial communication in the Linux that by nature supports only 8 bit serial communication. delay (around OS tick) arises. Our analysis shows that the cause is minimum length of waiting time to transmit data remained in Tx FIFO buffers. A modified Linux serial driver proposed in this paper decreases the delay less than 1ms by using accurate time delaying. Despite various system communication interfaces, enormous existing standards and system have adopted RS-232 serial communication, and the part of them have communicated by 9bit serial.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2025-2031
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• 1998

In moving picture coding standard MPEG2, a bit rate control system plays a key role for the compressing ratio and picture quality. We proposed a bit rate control scheme which assigns more bits to I, P frames and uses the average MQUANT of previous mackoblocks. The proposed scheme showed about 0.9dB improvement of image quality when compared to bit rate control method of MPEG2 Test-Model5.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.9
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• pp.799-808
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• 2012

Bit operation of scrambler in the WAVE System become less efficient because parallel processing is impossible in terms of hardware and software. In this paper, we propose algorism to find the starting position of the matrix table. Also, when bit operation algorithm of scrambler and algorithms for matrix table, algorithm used to find starting position of the matrix table were compared with the performance as 8 bit, 16bit, 32 bit processing units. As a result, the number of processing times per second could be done 2917.8 times more in an 8-bit, 5432.1 times in a 16-bit, 10277.8 times in a 32 bit. Therefore, algorithm to find the starting position of the matrix table improves the speed of the scrambler in the WAVE and the receiving speed of a variety of information gathering and precision over the Vehicle to Infra or Vehicle to Vehicle in the Intelligent Transport Systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.143-146
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• 2011

A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are $0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.739-743
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• 2013

In this paper, a two-dimensional (2-D) channel code for magnetic patterned media is proposed. Patterned media records an information bit on a magnetized dot. Since the space between adjacent tracks is narrow in order to increase the storage density, inter-track interference (ITI) and inter-symbol interference (ISI) can be problems. The amplitude of a bit signal can be corrupted by the 2-D ISI. The signal of the bit surrounded by the same value can be especially destructive, i.e. when its value is the same as the values of the eight surrounding bits. The proposed modulation coding scheme improves the decoding performance of patterned media by preventing this worst case and provides a better code rate than conventional channel codes.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.1
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• pp.33-40
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• 2014

In this paper we propose new image coding using wavelet transform. The new method constructs hierarchical bit plane and progressively transports each bit plane. The Proposed algorithm not only supports multi-resolution, dividing original image into special band and various resolution using Antonini's wavelet basis function but also reduces blocking effects that come into JPEG. In encoding time this algorithm considers each band characters and priority of transport order, and applies to fast search of image.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.787-794
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• 1999

This paper presents an ENMODL(enhances NORA MODL) circuit and implements a high-speed 32 bit CLA(carry lookahead adder) with the new dynamic logics. The proposed logic can reduce the area and the Propagation delay of carry because output inverters and a clocking PMOS of second stage can be omitted in two-stage MODL(multiple output domino logic) circuits. The 32-bit CLA is implemented with 0.8um double metal CMOS Process and the carry propagation delay of the adder is about 3.9 nS. The ENMODL circuits can improve the performance in the high-speed computing circuits depending on the degree of recurrence.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9C
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• pp.831-839
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• 2006

In this paper, we present an exact and general expression involving two-dimensional Gaussian Q-functions for the bit error rate (BER) of hierarchical MPSK with I/Q phase and amplitude imbalances over an additive white Gaussian noise (AWGN) channel. First we derive a BER expression for the k-th bit of hierarchical 4, 8, 16-PSK signal constellations when Gray code bit mapping is employed. Then, from the derived k-th bit BER expression, we present the exact and general average BER expression for hierarchical MPSK with I/Q phase and amplitude imbalances. This result can readily be applied to numerical evaluation for various cases of practical interest in an I/Q unbalanced hierarchical MPSK system, because the one- and two-dimensional Gaussian Q-functions can be easily and directly computed usinB commonly available mathematical software tools.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.579-585
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• 2006

In this study, we analysis an optical receivers using the optical preamplifier in a spectrum-sliced WDM systems. The average numbers of photons/bit, for an $10^{-9}$ error probability, counts using the OOK and FSK transmission. As a result, the theoretical sensitivity for PIN receiver and optical preamplifier receiver are approximately $9.2\times10^4\;and\;7.2\times10^2$ in the m=20, respectively. Also, the average numbers of photons/bit, for and given error probability, theoretical receiver sensitivity for Gaussian method and k-square method are approximately $9\times10^2\;and\;2.16\times10^2$ in the m=40, respectively. And the average numbers of photons/bit, for an given error probability, theoretical receiver sensitivity, OOK and FSK transmission are approximately $1.9\times10^2\;and\;3.1\times10^2$ in the m=20, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9B
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• pp.1092-1097
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• 2011

An anti-collision protocol which tries to minimize the collision probability and identification time is the most important factor in all identification technologies. This paper focuses on methods to improve the efficiency of tag's process in identification systems. Our scheme, Binary Slotted Query Tree (BSQT) algorithm, is a memoryless protocol that identifies an object's ID more efficiently by removing the unnecessary prefixes of the traditional Query Tree (QT) algorithm. With enhanced QT algorithm, the reader will broadcast 1 bit and wait the response from the tags but the difference in this scheme is the reader will listen in 2 slots (slot 1 is for 0 bit Tags and slot 2 is for 1 bit Tags). Base on the responses the reader will decide next broadcasted bit. This will help for the reader to remove some unnecessary broadcasted bits which no tags will response. Numerical and simulation results show that the proposed scheme decreases the tag identification time by reducing the overall number of request.