• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.10
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• pp.3458-3474
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• 2014

The performance of IEEE 802.11e enhanced distributed channel access (EDCA) is influenced by several interactive parameters that make quality of service (QoS) control complex and difficult. In EDCA, the most critical performance influencing parameters are the arbitration interframe space (AIFS) and contention window size (CW) of each access category (AC). The objective of this paper is to provide a scheme for parameter control such that the throughput per station as well as the overall system throughput of the network is maximized and controllable. For this purpose, a simple and accurate analytical model describing the throughput behavior of EDCA networks is presented in this paper. Based on this model, the paper further provides a scheme in which a Pareto optimal system configuration is obtained via an appropriate CW control for a given AIFS value, which is a different approach compared to relevant papers in the literature that deal with CW control only. The simulation results confirm the effectiveness of the proposed method which shows significant performance improvements compared to other existing algorithms.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.07a
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• pp.17-18
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• 2015

다중 안테나(MIMO, multi-input multi-output) 기법은 채널 용량을 증가시키기 위한 기술로써 최근 많이 연구되어 지고 있으며, DVB-T2, LTE 기술 및 802.11ac 등 방송, 이동통신 및 Wi-Fi 등 여러 분야에서 다양하게 쓰이고 있다. 그러나 다중 안테나 전송 기법은 송 수신 안테나 개수에 비례하여 채널 용량이 증가되므로, 채널 용량을 중가시키기 위해서는 많은 송 수신 안테나가 필요하다는 단점을 가지고 있다. 최근 다중 안테나 전송 기술과는 다른 방법으로 전송량을 증가시키는 기술인 FTN(faster than Nyquist) 전송 기법이 연구되고 있다. FTN 전송 기법은 동일한 대역폭에서 비트 오류 없이 정보를 전송할 수 있는 나이퀴스트(Nyquist) 심벌율보다 빠르게 심벌을 전송하는 기법으로 이론적으로 최대 20%까지 채널 용량을 증가시킬 수 있다. 그러므로 본 논문에서는 채널 용량을 증가시키기 위하여 다중 안테나 기법과 FTN 송신 기법을 연동하여 기존 다중 안테나 전송 기법의 단점을 보완하는 MIMO-FTN 전송 기법의 성능을 분석한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.387-389
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• 2015

IEEE 802.11e EDCA(Enhanced Distributed Channel Access)는 4개의 AC(Access Category)를 이용하여 트래픽에 따른 우선순위를 부여하고 QoS(Quality of Service)를 제공하기 위해 표준화되었다. EDCA는 이진 백오프 알고리즘을 갖는 CSMA/CA(Carrier Sense Multiple Access with Collision Avoidance) 방법을 이용한다. EDCA에서 패킷 전송에 실패할 경우 경쟁 윈도우 값은 두 배씩 증가 되고, 성공할 경우에는 최소 경쟁 윈도우 값으로 초기화된다. 따라서 경쟁 윈도우 값이 최적의 값을 유지하지 못해 많은 패킷 충돌을 야기하여 네트워크 성능을 감소시킨다. 이 문제를 해결하기 위해 기존에 제안된 논문에서는 패킷 전송 성공 후 경쟁 윈도우 값을 최소 경쟁 윈도우 값이 아닌 채널 혼잡 정도에 따라 계산된 값으로 설정한다. 그러나 이 방법은 트래픽 종류와 상관없이 같은 방법으로 동작하기 때문에 트래픽 종류에 따른 차별적 QoS를 보장하지 않는다. 또한 계산된 경쟁 윈도우 값은 현재 값에 비해 상대적으로 낮은 값을 갖기 때문에 여전히 높은 충돌율을 갖는다. 본 논문에서는 이 문제를 해결하기 위해 새로운 프로토콜을 제안한다. 제안된 방법에서는 네트워크의 혼잡 정도를 잘 반영하기 위한 새로운 경쟁 윈도우 계산 알고리즘을 제시한다. 또한 제안된 알고리즘은 트래픽 종류에 따른 QoS 보장을 위해 트래픽 종류에 따른 차별화 파라미터를 이용한다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.397-409
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• 2003

This paper describes an implementation of radix-4 trellis parallel architecture and backward state transition control trace back Viterbi decoder, and presents the application results to high speed wireless LAN. The radix-4 parallelized architecture Vietrbi decoder can not only improve the throughput with simple structure, but also have small processing delay time and overhead circuit compared to M-step trellis architecture one. Based on these features, this paper addresses a novel Viterbi decoder which is composed of branch metric computation, architecture of ACS and trace back decoding by sequential control of backward state transition for the implementation of radix-4 trellis parallelized structure. With the proposed architecture, the decoding of variable code rate due to puncturing the base code can easily be implemented by the unified Viterbi decoder. Moreover, any additional circuit and/or peripheral control logic are not required in the proposed decoder architecture. The trace back decoding scheme with backward state transition control can carry out the sequential decoding according to ACS cycle clock without additional circuit for survivor memory control. In order to evaluate the usefulness, the proposed method is applied to channel CODEC of the IEEE 802.11a high speed wireless LAN, and HDL coding simulation results are presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.12
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• pp.2353-2362
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• 2015

In this paper, we employ the single channel full duplex radio for wireless local area network (WLAN) systems, and design digital interference cancellers using adaptive signal processing. When the full duplex scheme is used for WLAN systems with multiple transmit and receive antennas, some interference is caused through the feedback of transmit signals from multiple antennas. To remove the feedback interference, we derive the least mean square (LMS), normalized LMS (NLMS), and recursive least squares (RLS) algorithms based on adaptive signal processing techniques. In addition, we analyze the theoretical convergence of the proposed LMS and RLS methods. The channel capacity of full duplex radios increases by two times than that of half duplex radios, when the packet error rate (PER) performances for the two systems are identical. Through numerical simulations in WLAN systems, it is shown that the full duplex method with the proposed interference cancellers has a similar PER performance with the conventional half duplex transmission scheme.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.75-81
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• 2015

This paper proposed the new eight-parallel MDC FFT processor using the eight-parallel MDC architecture and the efficient scheduling scheme. The proposed FFT processor supports the 256-point FFT based on the modified radix-$2^6$ FFT algorithm. The proposed scheduling scheme can reduce the number of complex multipliers from eight to six without increasing delay buffers and computation cycles. Moreover, the proposed FFT processor can be used in OFDM systems required high throughput and low hardware complexity. The proposed FFT processor has been designed and implemented with a 90nm CMOS technology. The experimental result shows that the area of the proposed FFT processor is $0.27mm^2$. Furthermore, the proposed eight-parallel MDC FFT processor can achieve the throughput rate up to 2.7 GSample/s at 388MHz.