• 한국멀티미디어학회논문지
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• 제19권8호
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• pp.1297-1309
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• 2016

In this paper, an efficient connected component labeling (CCL) method was proposed. The proposed method is based on GPU parallelism. The CCL is very important in various applications where images are analysed. However, the label of each pixel is dependent on the connectivity of adjacent pixels so that it is not very easy to be parallelized. In this paper, a GPU-based parallel CCL techniques were proposed and applied to the analysis of radar signal. Since the radar signals contains complex and large data, the efficiency of the algorithm is crucial when realtime analysis is required. The experimental results show the proposed method is efficient enough to be successfully applied to this application.

• 한국정보통신학회논문지
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• 제12권11호
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• pp.2045-2049
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• 2008

본 논문에서는 AMBA 기반으로 사용될 수 있는 H.264용 High Profile Intra Prediction을 구조를 제안한다. 설계된 모듈은 한 매크로 블록 당 최대 306 cycle내에 동작한다. 제안된 Encoder 구조를 검증하기 위하여 JM 13.2로부터 reference C를 개발하였으며, reference C로부터 test vector를 추출하여 설계된 회로를 검증하였다. 우리는 Hardware cost를 줄이기 위하여 plan mode를 제거 하였고, SAD 계산 방법과 8 pixel 병렬처리 등을 사용하여 Hardware cost와 cycle을 줄이는 방법을 채택하였다. 제안된 회로는 Full HD1080@fps 영상을 133MHz clock에서 동작시킬 수 있으며, 합성결과 TSMC 0.18um 공정에 램 포함 25만gate크기 이다.

• 대한전자공학회논문지
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• 제27권6호
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.