• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1702-1708
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• 2007

Dragon Stream Cipher is proposed for software base implementation in the eSTREAM project. Now this stream cipher is selected as a phase 3 focus candidate. Dragon is a new stream cipher contructed using a single word based NIFSR(non-linear feed back shift register) and 128/256 key/IV(Initialization Vector). Dragon is the keystream generator that produce 64bits of keystream. In this paper, we present an implementation of Drag(m stream cipher algorithm in hardware. Finally, the implementation is on Altera FPGA device, EP3C35F672I and the timing simulation is done on Altera's Quartus II. A result of 111MHz maximum clock rate and 7.1Gbps is throughput is obtained from the implementation.

• Journal of the Optical Society of Korea
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• v.8 no.2
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• pp.59-64
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• 2004

The response of a single-mode fiber to a sinusoidally modulated input has been studied to see its utility in measuring system performance in the presence of fiber nonlinearities. The sinusoidally modulated signal models an alternating bit sequence of ones and zeros in on-off keying. The sinusoidal response of normally dispersive fiber shows a strong correlation with eye-opening penalty (EOP) over a wide range of the nonlinearity parameter N (0.1 ＜ N$^2$＜ 100). This result implies that the measurement of the sinusoidal response can be an alternate way of measuring EOP without having a long sequence of randomly modulated input bits. But in the anomalous dispersion region, the sinusoidal response has a much more limited range of application to estimate system performance.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.130-139
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• 1994

Video compression algorithms are based on removing spatial and/or temproal redundancy inherent in image sequences by predictive(DPCM) encoding, transform encoding, or a combination of predictive and transform encoding. In this paper, each 8$\times$8 DCT coefficient of DFD(displaced frame difference) is adaptively quantized by one of the four quantizers depending on total distortion level, which is determined by characteristics of HVS(human visual system) and buffer status. Therefore, the number of possible quantizer selection vectors(patterns) is 4$^{64}$. If this vectors are coded, toomany bits are required. Thus, the quantizer selection vectors are limited to 2048 for Y and 512 for each U, V by the proposed method using SWAD(sum of weighted absolute difference) for discriminating vectors. The computer simulation results, using the codebook vectors which are made by the proposed method, show that the subjective and objective image quality (PSNR) are goor with the limited bit allocation. (17Mbps)

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.56-64
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• 1997

An HDTV frame has 4~6 times more pixels than a DTV frame. In order to encode the HDTV image in real time, parallel processing architectures have been widely used in many HDTV codec developments. That is, an HDTV Image is divided into several subbands and each subband is encoded in parallel using some DTV level encoders. In this paper, we adopt an HDTV codec architecture which divides an HDTV frame into 4 subbands and propose a new scene change detection algorithm using local variance. In addition, a new adaptive multichannel rate control scheme which allocate target bits adaptively to each subband of the HDTV image based on the activities of subband images is suggested in this paper. The activities of subband images are calculated at scene change detection part and reused at the adaptive rate control part. The simulation results show that the proposed scene change detection algorithm detects the scene change of HDTV video very accurately. Also the suggested adaptive multichannel rate control scheme shows better performance than the rate control method which allocates target bits equally to each subbands of the HDTV image.

• Journal of Communications and Networks
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• v.13 no.6
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• pp.602-611
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• 2011

The inter-domain routing scalability issue is a major challenge facing the Internet. Recent wide deployments of multihoming and traffic engineering urge for solutions to this issue. So far, tunnel-based proposals and compact routing schemes have been suggested. An implicit assumption in the routing community is that structured address labels are crucial for routing scalability. This paper first systematically examines the properties of identifiers and address labels and their functional differences. It develops a simple Internet routing model and shows that a binary relation T defined on the address label set A determines the cardinality of the compact label set L. Furthermore, it is shown that routing schemes based on flat address labels are not scalable. This implies that routing scalability and routing stability are inherently related and must be considered together when a routing scheme is evaluated. Furthermore, a metric is defined to measure the efficiency of the address label coding. Simulations show that given a 3000-autonomous system (AS) topology, the required length of address labels in compact routing schemes is only 9.12 bits while the required length is 10.64 bits for the Internet protocol (IP) upper bound case. Simulations also show that the ${\alpha}$ values of the compact routing and IP routing schemes are 0.80 and 0.95, respectively, for a 3000-AS topology. This indicates that a compact routing scheme with necessary routing stability is desirable. It is also seen that using provider allocated IP addresses in multihomed stub ASs does not significantly reduce the global routing size of an IP routing system.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3138-3147
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• 2000

EC(Electronic Commerce) which is cone the virtual space through Internet, has the advantage of time and space. On the contrary, it also has weak point like security probelm because anybody can easily access to the system due to open network attribute of Internet. Theretore, we need the solutions that protect the EC security problem for safe and useful EC activity. One of these solution is the implemonlation of a strong cipher algorithm. YK2(YoungKu Kang) cipher algorithm proposed in this paper is advantage for the EC security and it overcomes the limit of the current 6/1 bits block cipher algorithm using 128 bits key length for input, output, encryption key and 32 rounds. Moreover, it is degigned for the increase of time complexity and probability calculation by adapting more complex design for key scheduling regarded as one of the important element effected to enciyption.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.3
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• pp.75-84
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• 2004

In this paper, we present a related key differential attack on Full-round GOST Firstly, we present a distinguishing attack on full rounds of GOST, which can distinguish it from random oracle with probability 1- 64$2^{64}$ using a related key differential characteristic. We will also show that H. Seki et al.'s idea can be applied to attack on 31 rounds of GOST combining our related key differential characteristic. Lastly, we propose a related key differential attack on full rounds of GOST. In this attack we can recover 12 bits of the master key with $2^{35}$ chosen plaintexts and $2^{36}$ encryption times for the 91.7% expectation of success rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.253-256
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• 2009

This paper describes a core generator (FFT_Core_Gen) which generates Verilog HDL models of 8 different FFT/IFFT cores with $N=64{\times}2^k$($0{\leq}k{\leq}7$ for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture, and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage, and the internal data and twiddle factor has 14 bits. The generated FFT/IFFT cores have the SQNR of 58-dB for N=8,192 and 63-dB for N=64. The cores synthesized with a $0.35-{\mu}m$ CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed in $762.7-{\mu}s$, thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.10
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• pp.1093-1100
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• 2015

Since the security of RSA cryptosystem depends on the difficulty of factoring integers, it is the most important problem to factor large integers in RSA cryptosystem. The Lenstra elliptic curve factorization method(ECM) is considered a special purpose factoring algorithm as it is still the best algorithm for divisors not greatly exceeding 20 to 25 digits(64 to 83 bits or so). ECM, however, wastes most time to calculate $M{\cdot}P$ mod N and so Montgomery and Koyama both give fast methods for implementing $M{\cdot}P$ mod N. We, in this paper, further analyze Montgomery and Koyama's methods and propose an efficient algorithm which choose the optimal parameters and reduces the number of multiplications of Montgomery and Koyama's methods. Consequently, the run time of our algorithm is reduced by 20% or so than that of Montgomery and Koyama's methods.