• Journal of Broadcast Engineering
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• v.17 no.3
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• pp.480-490
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• 2012

When interpolating chrominance signal, the H.264/AVC standard uses linear interpolation. In this paper, we suggest more effective method that uses a high precision filter, 6-tap FIR filter, 2-tap linear filter for chroma interpolation. The experimental result shows that the proposed method achieves the BD-Rate decrease without the PSNR decrease compared with Jm11.0kta2.7. The maximum BD-rate improvements on Y component are 1.3%, those of Cb and Cr components are 19.8%, 25.0%, respectively. The average BD-rate improvements on Y component are 0.5%, those of Cb and Cr components are 6.1%, 6.9%, respectively.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.255-258
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• 2000

본 논문에서는 효율적인 면적의 저전력 FIR 필터를 제안한다. 제안된 필터는 6 비트 8 탭의 구조를 갖는PRML(Partial-Response Maximum Likelihood) 디스크드라이브 read channel용 FIR 필터이다 제안된 구조는 병렬연산 구조를 채택하고 있으며 네 단의 파이프라인 구조를 가지고 있다. 곱셈을 위하여 부스 알고리즘이 사용되며 압축기를 이용하여 덧셈을 수행한다. 저전력을 위해 CMOS 패스 트랜지스터를 사용하였으며 면적을 줄이기 위해 single-rail 로직을 사용하였다 제안된 구조를 0.65㎛ CMOS 공정을 이용하여 설계하였으며1.88 × 1.38㎟의 면적을 차지하였고 HSPICE 시뮬레이션 결과 3.3V의 공급전압에서 100㎒로 동작시 120㎽의 전력을 소모한다. 제안된 구조는 기존의 구조들에 비해 약 11%의 전력이 감소했으며 약 33%의 면적이 감소하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.464-472
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• 2012

In this paper, we propose a new super-resolution algorithm that uses successive frames by applying the block matching motion estimation algorithm. Usually, single frame super-resolution algorithms are based on probability or discrete wavelet transform (DWT) approach to extract high-frequency components of the input image, but only limited information is available for these algorithms. To solve this problem, various multiple-frame based super-resolution algorithms are proposed. The accuracy of registration between frames is a very important factor for the good performance of an algorithm. We therefore propose an algorithm using 6-Tap FIR filter to increase the accuracy of the image registration with sub-pixel unit. Proposed algorithm shows better performance than other conventional interpolation based algorithms such as nearest neighborhood, bi-linear and bi-cubic methods and results in about the same image quality as DWT based super-resolution algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.115-124
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• 2004

This paper proposes a high efficient and low power FIR filter chip for partial-response maximum likelihood (PRML) disk drive read channels; it is a 6-bit, 8-tap digital FIR filter. The proposed filter employs a parallel processing architecture and consists of 4 pipeline stages. It uses the modified Booth algorithm for multiplication and compressor logic for addition. CMOS pass-transistor logic is used for low power consumption and single-rail logic is used to reduce the chip area. The proposed filter is actually implemented and the chip dissipates 120mV at 100MHz, uses a 3.3V power supply and occupies 1.88 ${\times}$ 1.38 $\textrm{mm}^2$. The implemented filter requires approximately 11.7% less power compared with the existing architectures that use the similar technology.

• Journal of IKEEE
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• v.13 no.4
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• pp.110-115
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• 2009

The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation. The quarter-pixel interpolation is achieved using 6-tap horizontal or vertical FIR filters for luminance data and bilinear FIR filters for chroma data. We propose the architecture for interpolation of luminance and chroma data in H.264 decoders. It is composed of dual-channel pipelined processing elements and can interpolate integer-, half- and quarter-pixel data. The number of the processing cycles is different depending on the position. The processing elements are composed of adders and shifters to reduce the complexity while the accuracy of the pixel data are maintained. We design interpolators for luminance and chroma data using Verilog-HDL and verify the function and performance by implementing using an FPGA.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.341-350
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• 2003

In this paper, we evaluate the performance of a moving average (MA) channel estimation filter when space-time block coding transmit diversity (STBC-TD) is applied to the wideband direct sequence code division multiple access (WCDMA) forward link. And we present the infinite impulse response (IIR) filter scheme that can reduce the required memory buffer and the channel estimation delay time. This paper also compares the performance between MA filter scheme and IIR filter scheme in various Rayleigh fading channel environments through the bit error rate (BER) and the frame error rate (FER). Extensive computer simulation results show that transmission with STBC-TD provides a significant gain in performance over no transmit diversity technique, particularly at pedestrian speeds. If STBC-TD technique is employed in the channel estimator based on MA filter, it provides considerable performance gains against Rayleigh fading and reduces the optimum filter tap number. Consequently, the channel estimation delay time and the complexity of the receiver are reduced. In addition, the channel estimator based on IIR filter has the advantages such as little memory requirement and no delay time compared to the MA scheme. However, IIR filter coefficients is very sensitive to the mobile speed change and it exerts a serious influence upon the performance. For that reason, it is important to set uP the optimum IIR filter coefficients.

• Journal of Broadcast Engineering
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• v.10 no.4 s.29
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• pp.505-514
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• 2005

Image upsampling can be performed in both spatial and frequency (transform) domain. In the spatial domain, various upsampling techniques are developed and 6-tap FIR interpolation filter is most well known method, which is embedded in many video coding standards. It can provide high subjective quality but shows low objective quality. In the transform domain, simple zero padding method can produce upsampled image easily. It shows better objective quality than 6-tap filtering, but it yields ringing effects which annoy eyes. In this paper, we present efficient upsampling method using frequency addition method in transform domain to provide better subjective and objective quality than conventional method Extensive simulation results show that the proposed algorithm produces visually fine images with high PSNR.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.632-639
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• 2002

To reduce the area and power consumption in constant coefficient multiplications, the constant coefficient can be encoded using canonic signed digit(CSD) representation. When the partial product terms are added depending on the nonzero bit(1 or -1) positions in the CSD-encoded multiplier, all sign bits are properly extended before the addition takes place. In this paper, to reduce the overhead due to sign extension, a new method is proposed based on the fact that carry propagation in the sign extension part can be controlled such that a desired input bit can be propagated as a carry. Also, a fixed-width multiplier design method suitable for CSD multiplication is proposed. As an application, 43-tap filbert transformer for SSB/BPSK-DS/CDMA is implemented. It is shown that, about 16∼28% adders can be saved by the proposed method compared with the conventional methods.