• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.630-634
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• 2004

This paper describes the design of a two stage 1V power supply SiGe Low Noise Amplifier operating at 5.25 GHa for 802.lla wireless LAN application. The achieved performance includes a gain of 17 ㏈, noise figure of 2.7㏈, reflection coefficient of 15 ㏈, IIP3 of -5 ㏈m, and 1-㏈ compression point of -14㏈m. The total power consumption of the circuit was 7 mW including 0.5mW for the bias circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.393-396
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• 2018

Herein, a 94-GHz low-noise amplifier (LNA) using the 65-nm CMOS process is presented. The LNA is composed of a four-stage differential common-source amplifier and impedance matching is accomplished with transformers. The fabricated LNA chip shows a peak gain of 25 dB at 94 GHz and has a 3-dB bandwidth at 5.5 GHz. The chip consumes 46 mW of DC power from a 1.2-V supply, and the total chip area, including the pads, is $0.3mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12C
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• pp.759-763
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• 2011

In this paper, a dual-band T-shaped microstrip monopole antenna with a pair of slits for 2.4/5.2/5.8-GHz wireless local area networks (WLANs) is proposed. A pair of T-shaped slits is loaded on a T-shaped monopole antenna fed by microstrip line in order to obtain dual-band operation as well as to reduce the antenna size. It is demonstrated from experimental results that the proposed antenna can cover all the required bands for WLAN. The measured impedance bandwidth for VSWR<2 is about 5.7% (2.37-2.51GHz) in the lower frequency band and about 28.8% (4.76-6.35GHz) in the higher frequency band. The measured peak gains are about 1.33 dBi to 1.66 dBi in the 2.4GHz band, 3.50 dBi to 3.95 dBi in the 5.25GHz band, and 2.06 dBi to 2.34 dBi in the 5.8GHz band.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12A
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• pp.1183-1187
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• 2005

In this paper, a weathercock-shaped microstrip patch antenna for application in 5.25GHz band wireless LAN is designed and fabricated. To obtain sufficient bandwidth in VSWR<2, the T-slot is inserted on the patch, the coaxial probe source is used. The measured result of fabricated antenna obtained 350MHz or about $7.62\%$ bandwidth in VSWR<2 referenced to the center frequency, the gain of 5.25${\~}$6.70dBi. The experimental 3-dB beam width is shown to be broad across the pass band in azimuth and elevation at $80.32^{\circ}$ and $83.88^{\circ}$, in several.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.8
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• pp.42-50
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• 2007

This paper presents design methods for dual-frequency(2.4/5.8GHz) active receiving antennas. The proposed active receiving antennas are designed to interconnect the output port of a wideband antenna to the input port of an active device of High Electron Mobility Transistor directly and to receive RF signals of 2.4GHz and 5.2GHz simultaneously where the impedance matching conditions are optimized by adjusting the length of $1/20{\lambda}_0$(@5.8GHz) CPW transmission line in the planar antenna The bandwidth of implemented dual-frequency active receiving antennas is measured in the range of 2.0GHz to 3.1GHz and 5.25GHz to 5.9GHz. Gains are measured of 17.0dB at 2.4GHz and 15.0dB at 5.2GHz. The measured noise figure is 1.5dB at operating frequencies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.134-141
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• 2007

This paper presents a frequency synthesizer(FS) for 5.2GHz/2.4GHz dual band wireless applications which is designed in a standard $0.18{\mu}m$ CMOS1P6M process. The 2.4GHz frequency is obtained from the 5.2GHz output frequency of Voltage Controlled Oscillator (VCO) by using the Switched Capacitor (SC) and the divider-by-2. Power dissipations of the proposed FS and VCO are 25mW and 3.6mW, respectively. The tuning range of VCO is 700MHz and the locking time is $4{\mu}s$. The simulated phase noise of PLL is -101.36dBc/Hz at 200kHz offset frequency from 5.0GHz with SCA circuit on.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.476-478
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• 2006

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. In this paper a 64/65, 128/129 dual-modulus prescaler is designed using a $0.25{\mu}m$ CMOS process. In the design a new dynamic D-flip flop is employed, where glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The designed prescaler operates up to 2.5GHz and consumes 3.1mA at 2.5GHz operation.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.6
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• pp.1-12
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• 1999

This paper illustrates and analyzes system structure, link budget and cell coverage to accommodate Korea environment about LMDS systems that are expected to play an important role as the future wireless infrastructure of the information superhighway. In the mean time, many parameters used for the analysis apply to the allocated frequency bandwidth (Up-stream : 24.25GHz-24.75GHz, Down-stream : 25.5GHz-27.5GHz) of Ministry of Information and Communication. The modem and channel coding must be developed to accommodate specifications of DAVIC protocol. The materials about atmospheric phenomena refer to apply specifications of ITU-R. This paper will be need to disign the network structure and system configuration of LMDS system.

• Journal of Advanced Navigation Technology
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• v.25 no.6
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• pp.530-535
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• 2021

In this paper, the design method for a chipless RFID tag using ELC resonators is proposed. A four-bit chipless RFID tag is designed in a two by two array configuration using three ELC resonators with different resonant peak frequencies and one compact IDC resonator. The resonant peak frequency of the bistatic RCS for the IDC resonator is 3.125 GHz, whereas those of the three ELC resonators are adjusted to be at 4.225 GHz, 4.825 GHz, and 5.240 GHz, respectively, by using the gap between the capacitor-shaped strips in the ELC resonator. The spacing between the resonators is 1 mm. Proposed four-bit tag is fabricated on an RF-301 substrate with dimensions of 50 mm×20 mm and a thickness of 0.8 mm. It is observed from experiment results that the resonant peak frequencies of the fabricated four-bit chipless RFID tag are 3.290 GHz, 4.295 GHz, 4.835 GHz, and 5.230 GHz, respectively, which is similar to the simulation results with errors in the range between -2.3% and 0.2%.

• ETRI Journal
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• v.37 no.1
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• pp.21-25
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• 2015

A miniaturized triple-band antenna suitable for wireless USB dongle applications is proposed and investigated in this paper. The presented antenna, simply consisting of a circular-arc-shaped stub, an L-shaped stub, a microstrip feed line, and a rectangular ground plane has a compact size of $16mm{\times}38.5mm$ and is capable of generating three separate resonant modes with very good impedance matching. The measurement results show that the antenna has several impedance bandwidths for S11 ${\leq}$ -10 dB of 260 MHz (2.24 GHz to 2.5 GHz), 320 MHz (3.4 GHz to 3.72 GHz), and 990 MHz (5.1 GHz to 6.09 GHz), which can be applied to both 2.4/5.2/5.8 GHz WLAN bands and 3.5/5.5 GHz WiMAX bands. Moreover, nearly-omni-directional radiation patterns and stable gain across the operating bands can be obtained.