• Journal of Satellite, Information and Communications
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• v.10 no.1
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• pp.1-5
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• 2015

With the help of fast growing multimedia technology and high preference for users of large screens, the newest video coding standard, HEVC (High Efficiency Video Coding) high-quality video compression), has been introduced. Therefore, the high definition image services which are four times more clear than conventional HD video, are getting popular. JPEG 2000 also has stated to support 4K and 8K UHD. As a result, it requires fast processing technology to read and write UHD images. This paper introduces a study on fast parallel processing technology for UHD images. For this purpose, first, JPEG 2000 is reviewed and a GPU based parallel implementation is proposed for a preprocessing of color conversion stage. The parallelled algorithm is implemented with OpenCL (Open Computing Language). The simulation results show that the proposed method shows 5 times performance improvements on processing speed for 4K UHD over the method using threads.

• Broadcasting and Media Magazine
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• v.22 no.3
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• pp.30-38
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• 2017

2017년 5월 31일, 우리나라는 세계 최초 지상파 UHD(4K) 본 방송을 실시해 이제는 본격적인 디지털 UHD 방송 시대를 맞이하고 있다. UHDTV는 기존의 HD 영상에 비해 4배 이상 선명한 화질을 만들고 빛과 색을 처리하는데 민감하게 반응함으로 고품질의 영상을 구현하는데 조명의 역할은 상당히 크다고 할 수 있다. 따라서 UHD(Ultra High Definition) 영상의 가장 큰 장점인 고해상도의 화면구성을 위해 다양한 조명기구의 활용과 함께 부분적으로도 강조할 수 있는 섬세한 조명이 요구된다. 작품 전체에 있어 라이팅 밸런스와 통일성이 잘 조화를 이루도록 조정을 잘 해야만 UHD 영상이 가진 장점들을 잘 나타 낼 수 있다. UHD 영상의 넓어진 계조표현과 색대역의 특징을 보다 효과적으로 표현하기 위해서는 영화 조명과 같이 어두운 조명(Low Key Tone), 즉 화면의 일부분을 어둡게 하는 조명으로서 어두운 부분은 많고 밝은 부분이 적은 명암대비가 뚜렷한 조명연출을 예상한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.126-128
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• 2014

디지털 방송기술의 비약적인 발전으로 기존 HD(High Definition) 화질의 4~16배까지 지원 가능한 UHD(Ultra High Definition) 방송 서비스가 제공되는 새로운 시대를 맞이하게 되었다. UHD 방송은 초고선명 비디오와 22.2 채널 오디오 서비스가 가능한 차세대 실감방송 기술이다. 이러한 UHD 서비스를 제공하기 위해서는 고압축 영상 코덱 기술인 HEVC(High Efficiency Video Coding), OFDM(Othogonal Frequency Division Multiplexing) 기반 대용량 전송기술과 다양한 멀티미디어 부가서비스 가능한 전송 프로토콜이 필수적으로 요구된다. 최근 UHD 방송 전송 프로토콜로 표준화 추진 중인 MMT(MPEG Media Transport)는 이기종망에서 적용할 수 있으며, 양방향 전환이 가능하여 시청자의 요구사항을 실시간으로 반영할 수 있다는 장점을 지닌다. 한편, 지상파 UHD 방송 서비스를 빠르고 효과적으로 수신하기 위해 필요한 정보인 NIT(Network Information Table), RRT(Rating Region Table) 및 SDT(Service Description Table)가 MMT 시그널링 프로토콜에서는 포함되어 있지 않다. 따라서 본 논문에서는 지상파 UHD 방송 서비스의 효과적 수신이 가능한 MMT 기반 지상파 UHD 방송을 위해 NIT, RRT 및 SDT 정보가 포함된 서비스 시그널링 구조을 제안한다.

• Laser Solutions
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• v.17 no.4
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• pp.14-19
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• 2014

Laser beam was applied on the boundary of the polyurethane and biodegradable polyacetate polymers. The distributed laser passed through the polyurethane layer and heated the polyacetate layer, then the soften acetate was squeezed thorough the 1mm square slots of polyurethane for the mechanical joining. The surface roughness ranging between $0.28{\mu}m$ and $3.06{\mu}m$ had almost no effect on joining strength, but the optical properties of HD (High Definition) and UHD (Ultra High Definition) mode affected laser beam transmittance. The optimum laser power was found to be between 8watt and 10watt with 500mm/min of scanning speed. The joining boundary was characterized by optical and SEM analysis. Based on the experiment and characterization results, the laser energy was effective for the polymer joining and efficiency of joining.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.59-63
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• 2013

In this paper, the impact of the copper densities of substrate layers on IC package warpage is studied experimentally and numerically. The substrate strips used in this study contained two metal layers, with the metal densities and patterns of these two layers varied to determine their impacts. Eight legs of substrate strips were prepared. Leg 1 to leg 5 were prepared with a HD (high density) type of strip and leg 6 to leg 8 were prepared with UHD (ultra high density) type of strip. The top copper metal layer was designed to feature meshed patterns and the bottom copper layer was designed to feature circular patterns. In order to consider the process factors, the warpage of the substrate bottom was measured step by step with the following manufacturing process: (a) bare substrate, (b) die attach, (c) applying mold compound (d) and post reflow. Furthermore, after the post reflow step, the substrate strips were diced to obtain unit packages and the warpage of the unit packages was measured to check the warpage trends and differences. The experimental results showed that the warpage trend is related to the copper densities. In addition to the experiments, a Finite Element Modeling (FEM) was used to simulate the warpage. The nonlinear material properties of mold compound, die attach, solder mask, and substrate core were included in the simulation. Through experiment and simulation, some observations were concluded.

• Journal of Broadcast Engineering
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• v.20 no.4
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• pp.497-508
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• 2015

Current communication networks consist of channels with various throughputs, protocols, and packet loss rates. Moreover, there are also diverse user multimedia consumption devices having different capabilities and screen sizes. Thus, a practical necessity of scalability on video coding have been gradually increasing. Recently, The Scalable High Efficiency Video Coding(SHVC) standard is developed by Joint Collaborative Team on Video Coding(JCT-VC) organized in cooperation with MPEG of ISO/IEC and VCEG of ITU-T. This paper introduces coding tools of SHVC including adopted and unadopted tools discussed in the process of the SHVC standardization. Furthermore, the individual tool and combined tool set are evaluated in terms of coding efficiency relative to a single layer coding structure. This analysis would be useful for developing a fast SHVC encoder as well as researching on a new scalable coding tool.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.416-419
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• 2015

In this paper, we propose an effective design of transform hardware for real-time HEVC(High Efficiency Video Coding) encoder. HEVC encoder determines the transform mode($4{\times}4$, $8{\times}8$, $16{\times}16$, $32{\times}32$) by comparing RDCost. RDCost require a significant amount of computation and time because it is determined by bit-rate and distortion which is computated via transform, quantization, dequantization, and inverse transform. This paper therefore proposes a new method for transform mode determination using sum of transform coefficient. Also, proposed hardware architecture is implemented with multiplexer, recursive adder/subtracter, and shifter only to derive reduction of the computation. Proposed method for transform mode determination results in an increase of 0.096 in BD-PSNR, 0.057 in BD-Bitrate, and decrease of 9.3% in encoding time by comparing HM 10.0. The hardware which is proposed is implemented by 256K logic gates in TSMC 130nm process. Its maximum operation frequency is 200MHz. At 140MHz, the proposed hardware can support 4K Ultra HD video encoding at 60fps in real time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.755-758
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• 2014

In this paper, we propose effective Deblocking Filter hardware architecture for High Efficiency Video Coding encoder. we propose Deblocking Filter hardware architecture with less processing time, filter ordering for low area design, effective memory architecture and four-pipeline for a high performance HEVC(High Efficiency Video Coding) encoder. Proposed filter ordering can be used to reduce delay according to preprocessing. It can be used for realtime single-port SRAM read and write. it can be used in parallel processing by using two filters. Using 10 memory is effective for solving the hazard caused by a single-port SRAM. Also the proposed filter can be used in low-voltage design by using clock gating architecture in 4-pipeline. The proposed Deblocking Filter encoder architecture is designed by Verilog HDL, and implemented by 100k logic gates in TSMC $0.18{\mu}m$ process. At 150MHz, the proposed Deblocking Filter encoder can support 4K Ultra HD video encoding at 30fps, and can be operated at a maximum speed of 200MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.295-298
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• 2014

In this paper, an efficient design of HEVC Adaptive Loop Filter(ALF) for filter coefficients estimation is proposed. The ALF performs Cholesky decomposition of $10{\times}10$ matrix iteratively to estimate filter coefficients. The Cholesky decomposition of the ALF consists of root and division operation which is difficult to implement in a hardware design because it needs to many computation rate and processing time due to floating-point unit operation of large values of the Maximum 30bit in a LCU($64{\times}64$). The proposed hardware architecture is implemented by designing a root operation based on Cholesky decomposition by using multiplexer, subtracter and comparator. In addition, The proposed hardware architecture of efficient and low computation rate is implemented by designing a pipeline architecture using characteristic operation steps of Cholesky decomposition. An implemented hardware is designed using Xilinx ISE 14.3 Vertex-6 XC6VCX240T FPGA device and can support a frame rate of 40 4K Ultra HD($4096{\times}2160$) frames per second at maximum operation frequency 150MHz.