• Journal of Drive and Control
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• v.19 no.1
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• pp.43-50
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• 2022

The aim of this study was to conduct basic research on the development of a dual-clutch transmission(DCT) and automatic transmission for agricultural tractors. The DCT layout and the DCT simulation model were developed using commercial software. Power transmission efficiency of the DCT and component power loss were analyzed to verify the developed simulation model. Power loss analysis of the components was conducted according to previous studies and ISO(International Organization for Standardization) standards. The power transmission efficiency of the DCT simulation model was 68.4-91.5% according to the gear range. The power loss in the gear, bearing, and clutch DCT system components was 0.75-1.49 kW, 0.77-2.99 kW, and 5.24-10.52 kW, respectively. The developed simulation model not include the rear axle, differential gear, final reduction gear. Therefore actual power transmission efficiency of DCT will be decreased. In a future study, an actual DCT can be developed through the simulation model in this study, and optimization design of DCT can be possible by comparing simulation results and actual vehicle test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6C
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• pp.602-608
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• 2003

In this paper, we propose an efficient DCT calculation method for fast video encoding. We show that the SAD obtained in the motion estimation and compensation process is decomposed into the positive and negative terms. Based on a theoretical analysis, it is shown that the DCT calculation is classified into 4 cases - DCT Skip, Reduced_DCT1 , Reduced_DCT2, and original DCT- according to the positive and negative terms. In the proposed algorithm, one of 4 cases is used for DCT in order to reduce the computational complexity. The simulation results show that the proposed algorithm achieves computational saving approximately 25.2% without image degradation and computational overhead.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.371-372
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• 2007

In this paper we present performance and implementation comparisons of high performance two dimensional forward and inverse Discrete Cosine Transform (2D-DCT/IDCT) algorithm and low power algorithm for $8{\times}8$ 20 DCT and quantization based on partial sum and its corresponding hardware architecture for FPGA in MPEG-4. The architecture used in both low power 20 DCT and 2D IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic(DA) technique to implement the DCT/IDCT reduces the hardware complexity. The design was made using Mentor Graphics Tools for design entry and implementation. Mentor Graphics ModelSim SE6.1f was used for Verilog HDL entry, behavioral Simulation and Synthesis. The 2D DCT/IDCT consumes only 50% of the Operating Power.

• Journal of the Korea Computer Industry Society
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• v.4 no.4
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• pp.433-442
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• 2003

The performance of communication systems should be tested against a set of requirements. To this end, noise generation systems are used to generate noise signals with specified characteristics. In recent study, noise generation system using DCT outperforms the conventional noise generation system when a noise model requires complicated PSD(Power Spectral Density) specifications. In this paper low area/power structures of non-DCT block in DCT-based noise generation system are proposed. Simulation results show that the low area structure results in area reduction by 61-64% and the low power structure achieves power reduction by 88-89% except DCT blocks.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1265-1274
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• 1990

A new classified VQ scheme for DCT coefficients(DCT-CVQ) is proposed for still image coding. DCT coefficient matrices are classified into six classes by ac coefficients that well represent edge characteristics and the distribution of ac energy in the DCT domain. To reduce the complexity of, VQ, ac transform coefficients are partitioned into several vectors, and an adaptive method is provided by making different codebook sizes for different classes. Simulation results show that this DCT-CVQ results in good subjective quality at low bit rates, and SNR is increased by about 1.5-4.0 dB in the range 0.2-0.5 bpp, when compared with other DCT-VQ coding schemes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.571-574
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• 2001

In our paper, We propose an efficient adaptive coding method using kohonen neural network. An efficient adaptive encoding method using Kohonen net work is discribed through the analysis of those compression methods with the application of the neural network. In order to increase the compression ratio, a image is first divided into 8*8 subimages, then all subimages are transformed by DCT. These DCT sub-blocks are divided into N(4) classes by Kohonen network. Hits are distributed according to the variance of the DCT sub-block. Thus we get N(4)bit allocation matrices. Excellent performance is shown by the computer simulation. so we found that our proposed method is better then classifing subimages by AC energy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.497-505
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• 2016

The two-dimensional (2D) Discrete Cosine Transform (DCT) is used widely in image and video processing systems. The perception of human visualization permits us to design approximate rather than exact DCT. In this paper, we propose a digital implementation of 16-point approximate 2D DCT architecture based on one-dimensional (1D) DCT and Modified Gate Diffusion Input (MGDI) technique. The 8-point 1D Approximate DCT architecture requires only 12 additions for realization in digital VLSI. Additions can be performed using the proposed 8 transistor (8T) MGDI Full Adder which reduces 2 transistors than the existing 10 transistor (10T) MGDI Full Adder. The Approximate MGDI 2D DCT using 8T MGDI Full adders is simulated in Tanner SPICE for $0.18{\mu}m$ CMOS process technology at 100MHZ.The simulation result shows that 13.9% of area and 15.08 % of power is reduced in the 8-point approximate 2D DCT, 10.63 % of area and 15.48% of power is reduced in case of 16-point approximate 2D DCT using 8 Transistor MGDI Full Adder than 10 Transistor MGDI Full Adder. The proposed architecture enhances results in terms of hardware complexity, regularity and modularity with a little compromise in accuracy.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.4
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• pp.331-341
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• 1991

The discrete cosine transform (DCT) is widely used in many signal processing areas, including image and speech data compression. In this paper, we investigate a fixed-point error analysis for fast DCT algorithms, namely, Lee [6], Hou [7] and Vetterli [8]. A statistical model for fixed-point error is analyzed to predict the output noise due to the fixed-point implementation. This paper deals with two's complement fixed-point data representation with truncation and rounding. For a comparison purpose, we also investigate the direct form DCT algorithm. We also propose a suitable scaling model for the fixed-point implementation to avoid an overflow occurring in the addition operation. Computer simulation results reveal that there is a close agreement between the theoretical and the experimental results. The result shows that Vetterli's algorithm is better than the other algorithms in terms of SNR.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.152-161
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• 1996

This paper descrisbes the implementation of a 20D DCT that can be used for video conference, JPEG, and MPEG-related applications. The implemented DCT consists of two 1-D DCTs and a transposed memory between them, and uses ROM-based multipliers instead of conventional ones. As the system bit length, the minimum bit length that satisfies the accuracy specified by the ITU standard H.261 was chosen through the simulations using the C language. The proposed design uses a dual port RAM for the transposed memory, and processes two bits of input-pixel data simultaneously t ospeed up addition process using two sets of ROMs. The basic system architecture was designed using th Synopsys schematic editor, and internal modules were described in VHDL and synthesized to logic level after simulation. Then, the compass silicon compiler was used to create the final lyout with 0.8um CMOS libraries, using the standard cell approach. The final layout contains about 110, 000 transistors and has a die area of 4.68mm * 4.96mm, and the system has the processing speed of about 50M pixels/sec.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9C
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• pp.697-703
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• 2008

The H.264/AVC video coding standard provides higher coding efnciency compared to the conventional MPEG-2 standard. Since a lot of videos have been encoded using MPEG-2, the format conversion from MPEG-2 to H.264 is essential. In this paper, we propose an efficient method for the conversion of DCT coefficients to H.264/AVC transform coefficients. This conversion is essential, since $8{\times}8$ DCT and $4{\times}4$ integer transform are used in MPEG-2 and H.264/AVC, respectively. The mathematical analysis and computer simulation show that the computational complexity of the proposed algorithm is reduced compared to the conventional algorithm, while the loss caused by the conversion is negligible.