• 박물관보존과학
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• 제31권
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• pp.39-54
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• 2024

솜포 포장재를 이용해 수작업으로 이루어지는 도자기 포장 기술을 3차원 디지털 기술로의 대체 가능성을 확인해 보고자 하였다. TPU 소재를 이용해 출력한 3D 포장재의 충격 흡수성과 내진동성, 압축 저항성 확인을 위해 복합진동, 포장압축, 포장낙하 시험을 진행하였다. 시험 결과 3D 포장재가 복합진동시험 감쇠비 기준 약 10~20% 증진된 내진동성을 가지고, 약 5배 이상의 압축 저항 성능을 보여주었으며, 6면의 낙하 시험에서 파손되지 않아 충격 흡수 성능도 향상된 것을 확인하였다. 이러한 결과 도자기 포장재의 재사용성을 확보하고 포장 기법을 간소화할 수 있으며, 포장재 및 포장 기술의 다양성을 제시할 수 있을 것으로 판단된다.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• 월간포장계
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• 통권296호
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• pp.67-72
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• 2017

• 월간포장계
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• 통권296호
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• pp.77-80
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• 2017

• 월간포장계
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• 통권330호
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• pp.100-107
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• 2020

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2005년도 ISMP
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• pp.23-34
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• 2005

Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP ('above' passivation), approach and a foundry level ('below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail.

• 월간포장계
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• 통권213호
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• pp.80-84
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• 2011

• 마이크로전자및패키징학회지
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• 제29권4호
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• pp.1-8
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• 2022

TSV 기술을 포함한 고밀도, 고집적 패키징 기술은 IoT, 6G/5G 통신, HPC (high-performance computing)등 여러 분야에서 중요한 기술로 여겨지고 있다. 2차원에서 고집적화를 달성하는 것은 물리적 한계에 도달하게 되었으며, 따라서 3D 패키징 기술을 위하여 다양한 연구들이 진행되고 있다. 본 고에서는 scallop의 형성 원인과 영향, 매끈한 측벽을 만들기 위한 scallop-free 에칭 기술, TSV 표면의 Cu bonding에 대해서 자세히 조사하였다. 이러한 기술들은 고품질 TSV 형성 및 3D 패키징 기술에 영향을 줄 것으로 예상한다.

• 월간포장계
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• 통권262호
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• pp.54-65
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• 2015

• 마이크로전자및패키징학회지
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• 제15권1호
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• pp.39-44
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• 2008

In this paper, fully embedded 2.4GHz WLAN band pass filter (BPF) was investigated into a multi-layered organic packaging substrate using high Q spiral stacked inductors and high Dk MIM capacitors for low cost RF System on Package (SOP) applications. The proposed 2.4GHz WLAN BPF was designed by modifying chebyshev second order filter circuit topology. It was comprised of two parallel LC resonators for obtaining two transmission zeros. It was designed by using 2D circuit and 3D EM simulators for finding out optimal geometries and verifying their applicability. It exhibited an insertion loss of max -1.7dB and return loss of min -l7dB. The two transmission zeros were observed at 1.85 and 6.7GHz, respectively. In the low frequency band of $1.8GHz{\sim}1.9GHz$, the stop band suppression of min -23dB was achieved. In the high frequency band of $4.1GHz{\sim}5.4GHz$, the stop band suppression of min -l8dB was obtained. It was the first embedded and the smallest one of the filters formed into the organic packaging substrate. It has a size of $2.2{\times}1.8{\times}0.77mm^3$.