• Conservation Science in Museum
• /
• v.31
• /
• pp.39-54
• /
• 2024

We wanted to check The feasibility of substituting the manual ceramic packaging technology with 3D digital technology using cotton pad packaging material was examined. To examine the shock absorption, vibration resistance and compression resistance of 3D packaging material printed out by using TPU material, composite vibration, and packaging compression and drop tests were conducted. As the results of the tests, the 3D packaging material displayed vibration resistance that has been improved by approximately 10~20% based on the damping ratio of the composite vibration test, compression resistance performances that are more than 5 times higher, and shock absorption performance was also improved as the packaged object was not broken in the six-sided drop test. Based on these results, it is determined that it would be possible to secure the reusability of the ceramic packaging materials and simplify packaging techniques, and to present diversity in the packaging materials and packaging technologies.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.38-47
• /
• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• The monthly packaging world
• /
• s.296
• /
• pp.67-72
• /
• 2017

• The monthly packaging world
• /
• s.296
• /
• pp.77-80
• /
• 2017

• The monthly packaging world
• /
• s.330
• /
• pp.100-107
• /
• 2020

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2005.09a
• /
• pp.23-34
• /
• 2005

Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP ('above' passivation), approach and a foundry level ('below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail.

• The monthly packaging world
• /
• s.213
• /
• pp.80-84
• /
• 2011

• Journal of the Microelectronics and Packaging Society
• /
• v.29 no.4
• /
• pp.1-8
• /
• 2022

High-density packaging technologies, including Through-Si-Via (TSV) technologies, are considered important in many fields such as IoT (internet of things), 6G/5G (generation) communication, and high-performance computing (HPC). Achieving high integration in two dimensional packaging has confronted with physical limitations, and hence various studies have been performed for the three-dimensional (3D) packaging technologies. In this review, we described about the causes and effects of scallop formation in TSV, the scallop-free etching technique for creating smooth sidewalls, Cu pillar and Cu-SiO₂ hybrid bonding in TSV. These technologies are expected to have effects on the formation of high-quality TSVs and the development of 3D packaging technologies.

• The monthly packaging world
• /
• s.262
• /
• pp.54-65
• /
• 2015

• Journal of the Microelectronics and Packaging Society
• /
• v.15 no.1
• /
• pp.39-44
• /
• 2008

In this paper, fully embedded 2.4GHz WLAN band pass filter (BPF) was investigated into a multi-layered organic packaging substrate using high Q spiral stacked inductors and high Dk MIM capacitors for low cost RF System on Package (SOP) applications. The proposed 2.4GHz WLAN BPF was designed by modifying chebyshev second order filter circuit topology. It was comprised of two parallel LC resonators for obtaining two transmission zeros. It was designed by using 2D circuit and 3D EM simulators for finding out optimal geometries and verifying their applicability. It exhibited an insertion loss of max -1.7dB and return loss of min -l7dB. The two transmission zeros were observed at 1.85 and 6.7GHz, respectively. In the low frequency band of $1.8GHz{\sim}1.9GHz$, the stop band suppression of min -23dB was achieved. In the high frequency band of $4.1GHz{\sim}5.4GHz$, the stop band suppression of min -l8dB was obtained. It was the first embedded and the smallest one of the filters formed into the organic packaging substrate. It has a size of $2.2{\times}1.8{\times}0.77mm^3$.