• Proceedings of the KIEE Conference
• /
• 1997.11a
• /
• pp.479-483
• /
• 1997

In general, motor parameters can be divided into mechanical/electrical parameters and harmonic parameters. Mechanical/electrical parameters identification of motor have been studying systematically for a long time. But, systematical study on harmonic parameters analysis for efficient motor drive system are very poor. The goal of this paper is to propose analyzing method of harmonic parameters for motor drive system with various experimental graphic screens and numerical results and to develope harmonic parameters analyzer. A developed analyzer is made up 586-PC and DSP (digital signal processor) board, motor drive system, power and harmonic parameters analyzing software for windows. Harmonic parameters are analyzed using correlation signal processing techniques based on the correlation between voltage and current waveforms. Analysis results are visualized by 3-D current coordinates, and it is compared and evaluated with conventional time/frequency domain. To verify the validity of the proposed system, 1/4HP capacitor run type single phase induction motor and thyristor speed controller is used for analyzing. Harmonic parameters of motor drive system is analyzed and verified, with varying fire angle of thyristor speed controller, and the proposed approach is to confirm validity.

• Journal of Broadcast Engineering
• /
• v.16 no.4
• /
• pp.596-601
• /
• 2011

In this paper, we propose a fast depth-image-based rendering method to generate a virtual view image in real-time using a graphic processor unit (GPU) for a 3D broadcasting system. Before the transmission, we encode the input 2D+depth video using the H.264 coding standard. At the receiver, we decode the received bitstream and generate a stereo video using a GPU which can compute in parallel. In this paper, we apply a simple and efficient hole filling method to reduce the decoder complexity and reduce hole filling errors. Besides, we design a vertical parallel structure for a forward mapping process to take advantage of the single instruction multiple thread structure of GPU. We also utilize high speed GPU memories to boost the computation speed. As a result, we can generate virtual view images 15 times faster than the case of CPU-based processing.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.11
• /
• pp.101-109
• /
• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.