• 제목/요약/키워드: 3D Packaging

검색결과 422건 처리시간 0.028초

나노기술 적용을 통한 포장 분야의 전망 (Expectation of Nanotechnology Applications in Packaging)

  • 김재능;이윤석
    • 한국포장학회지
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    • 제12권1호
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    • pp.27-34
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    • 2006
  • Nanotechnology is playing an increasingly important role in the development on most areas of science and technology. Because of its potential of providing novel performance at the nanoscale, the nanotechnology can influence a wide range of applications such as information, energy, environment and biology, all essential for socioeconomic development in the near future. In the packaging industry, the main applications of nanotechnology are (1) to enhance durability, (2) improve gas and oxygen barriers of raw materials for films and packaging, (3) create new functional sensors, and (4) lengthen shelf life for the packaged food quality and will also help in pharmaceuticals and cosmetics. Nanotechnology is growing in an international interactions which accelerate in science, education, and industrial R&D. Government, industries and the business sector in Korea have shown a strong ambition towards the development of nanotechnology for the future. Meanwhile, a strategic investment in packaging area is much smaller compared to supporting research and development (R&D) of various major research areas. This article were reviewed the status and trends of current packaging research and development activities using nanotechnology in Korea, USA, Japan, and other international nations.

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Overview of High Performance 3D-WLP

  • Kim, Eun-Kyung
    • 한국재료학회지
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    • 제17권7호
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    • pp.347-351
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    • 2007
  • Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

저온 Cu-Cu본딩을 위한 12nm 티타늄 박막 특성 분석 (Evaluation of 12nm Ti Layer for Low Temperature Cu-Cu Bonding)

  • 박승민;김윤호;김사라은경
    • 마이크로전자및패키징학회지
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    • 제28권3호
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    • pp.9-15
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    • 2021
  • 최근 반도체 소자의 소형화는 물리적 한계에 봉착했으며, 이를 극복하기 위한 방법 중 하나로 반도체 소자를 수직으로 쌓는 3D 패키징이 활발하게 개발되었다. 3D 패키징은 TSV, 웨이퍼 연삭, 본딩의 단위공정이 필요하며, 성능향상과 미세피치를 위해서 구리 본딩이 매우 중요하게 대두되고 있다. 본 연구에서는 대기중에서의 구리 표면의 산화방지와 저온 구리 본딩에 티타늄 나노 박막이 미치는 영향을 조사하였다. 상온과 200℃ 사이의 낮은 온도 범위에서 티타늄이 구리로 확산되는 속도가 구리가 티타늄으로 확산되는 속도보다 빠르게 나타났고, 이는 티타늄 나노 박막이 저온 구리 본딩에 효과적임을 보여준다. 12 nm 티타늄 박막은 구리 표면 위에 균일하게 증착되었고, 표면거칠기(Rq)를 4.1 nm에서 3.2 nm로 낮추었다. 티타늄 나노 박막을 이용한 구리 본딩은 200℃에서 1 시간 동안 진행하였고, 이후 동일한 온도와 시간 동안 열처리를 하였다. 본딩 이후 측정된 평균 전단강도는 13.2 MPa이었다.

3차원 적층 패키지를 위한 ISB 본딩 공정의 파라미터에 따른 파괴모드 분석에 관한 연구 (Fracture Mode Analysis with ISB Bonding Process Parameter for 3D Packaging)

  • 이영강;이재학;송준엽;김형준
    • Journal of Welding and Joining
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    • 제31권6호
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    • pp.77-83
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    • 2013
  • 3D packaging technology using TSV (Through Silicon Via)has been studied in the recent years to achieve higher performance, lower power consumption and smaller package size because electrical line is shorter electrical resistivity than any other packaging technology. To stack TSV chips vertically, reliable and robust bonding technology is required because mechanical stress and thermal stress cause fracture during the bonding process. Cu pillar/solder ${\mu}$-bump bonding process is usually to interconnect TSV chips vertically although it has weak shape to mechanical stress and thermal stress. In this study, we suggest Insert-Bump (ISB) bonding process newly to stack TSV chips. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure. After ISB bonding, we observed microstructure of bump joint by SEM and then evaluated properties of bump joint by die shear test.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • 이강욱
    • 마이크로전자및패키징학회지
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    • 제22권2호
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Current Status of Semiconductor and Microelectronic Packaging Technology Development in Korea

  • Sun, Yong-Bin
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2002년도 춘계 기술심포지움 논문집
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    • pp.1-6
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    • 2002
  • It is very important to foresee the main stream of technology development in the future. Packaging related manufacturers in equipment and materials focused their strength on products sharing big portion of world markets. As a result, domestic supply sources for packaging materials and equipment has been increased, but the manufacturer's capital and manpower is so limited to develop high technology machinery and high functional materials. The current status of packaging infrastructures in Korea is reviewed statistically. The hot issues in packaging arena are now in wafer level packaging, 3D packaging, and ultra-thin packaging. In addition, the recent advancement in microelectronics packaging technology is also covered.

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전력 무결성을 위한 온 칩 디커플링 커패시터 (On-chip Decoupling Capacitor for Power Integrity)

  • 조승범;김사라은경
    • 마이크로전자및패키징학회지
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    • 제24권3호
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    • pp.1-6
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    • 2017
  • As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

3차원 인쇄기술을 이용한 전자소자 연구 동향 (3D Printed Electronics Research Trend)

  • 박예슬;이주용;강승균
    • 마이크로전자및패키징학회지
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    • 제28권2호
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    • pp.1-12
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    • 2021
  • 3차원 인쇄 기술은 제품의 설계를 3차원으로 하여 조립없이 제품의 생산까지의 시간을 획기적으로 줄이고 복잡한 구조도 구현할 수 있어 미래의 기술로 각광받고 있다. 본 논문은 3차원 인쇄기술을 이용한 전자소자에 대한 최근 연구동향을 알아보면서 구성품, 전원공급장치와 회로에서의 연결과 3차원 인쇄기술 PCB의 응용한 연구논문들을 소개하고 있다. 3차원 인쇄기술로 제작한 전자소자는 원스톱으로 전자소자, 솔더링(soldering), 스태킹(stacking), 회로의 봉지막(encapsulation)까지 제작함으로써 생산설비의 단순화와 전자기기를 개인 맞춤형을 할 수 있는 가능성을 보여주었다.

MCM-D 공정기술을 이용한 V-BAND FILTER 구현에 관한 연구 (V-Band filter using Multilayer MCM-D Technology)

  • 유찬세;송생섭;박종철;강남기;차종범;서광석
    • 대한전자공학회논문지SD
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    • 제43권9호
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    • pp.64-68
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    • 2006
  • 본 연구에서는 Si bump를 이용해 기판의 기계적, 열적 특성을 개선한 MCM-D 기판공정을 개발하였고, 이를 system-on-package(SOP)-D개념의 system 구현에 적용하고자 하였다. 이 과정에서 밀리미터파 대역에 적용될 수 있는 필터를 설계하고 구현하여 그 특성을 관찰하였다. 두 가지 형태의 필터를 구현하였는데 첫 번째는 공진기간의 커플링을 이용한 구조로서 2층의 금속층과 3층의 유전체(BCB)를 이용하였다. 구현된 필터 특성은 중심주파수 55 GHz에서의 삽입손실이 2.6 dB이고 군지연이 0.06 ns정도로 우수한 특성을 나타내었다. 또한 일반적으로 알려진coupled line 형태의 필터를 구현하였는데 삽입손실이 3 dB, 군지연이 0.1 ns정도의 특성을 나타내었다. 이렇게 내장형 필터를 포함한 MCM-D 기판은 MMIC를 flip-chip 방법으로 실장 할 수 있어서 집적화된 밀리미터파 대역 초소형 system 구현에 적용되어 우수한 특성을 나타낼 것으로 기대된다.

IMT-2000단말기용 RF 수신모듈 설계 및 제작에 관한 연구 (A Study on the Design and Fabrication of RF Receiver Module for IMT-2000 Handset)

  • 이규복;송희석;박종철
    • 마이크로전자및패키징학회지
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    • 제7권3호
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    • pp.19-25
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    • 2000
  • 본 논문에서는 5 MHz의 채널 대역폭을 갖는 IMT-2000단말기용 RF 수신모듈을 설계하여 제작하였다. 제작된 RF수신모듈은 저잡음증폭기, RF SAW필터, 하향 변환기, IF SAW필터, AGC, PLL 주파수합성기로 구성되어졌다. 저잡음증폭기의 잡음지수와 IIP3는 2.14 GHz에서 0.8 dB와 3 dBm이고, 하향 변환기의 변환이득은 10 dB, AGC의 활성영역은 80 dB이었고, PLL의 위상잡음은 100 kHz에서 -100 dBc이였다. 수신모듈의 수신감도는 -48 dBm으로 제작되었다.

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